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Commit 23946ef1 authored by Ralf Baechle's avatar Ralf Baechle
Browse files

MIPS: Move gas macro MAPPED_KERNEL_SETUP_TLB to IP27-specific code. 



It's IP27-specific and can only cause trouble in head.S.

Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 27f62b9f

arch/mips/include/asm/mach-ip27/kernel-entry-init.h

+39 −0
Original line number Diff line number Diff line
@@ -23,6 +23,45 @@ 
	dsrl	\res, NSRI_NODEID_SHFT

	.endm



	/*

	 * inputs are the text nasid in t1, data nasid in t2.

	 */

	.macro MAPPED_KERNEL_SETUP_TLB

#ifdef CONFIG_MAPPED_KERNEL

	/*

	 * This needs to read the nasid - assume 0 for now.

	 * Drop in 0xffffffffc0000000 in tlbhi, 0+VG in tlblo_0,

	 * 0+DVG in tlblo_1.

	 */

	dli	t0, 0xffffffffc0000000

	dmtc0	t0, CP0_ENTRYHI

	li	t0, 0x1c000		# Offset of text into node memory

	dsll	t1, NASID_SHFT		# Shift text nasid into place

	dsll	t2, NASID_SHFT		# Same for data nasid

	or	t1, t1, t0		# Physical load address of kernel text

	or	t2, t2, t0		# Physical load address of kernel data

	dsrl	t1, 12			# 4K pfn

	dsrl	t2, 12			# 4K pfn

	dsll	t1, 6			# Get pfn into place

	dsll	t2, 6			# Get pfn into place

	li	t0, ((_PAGE_GLOBAL|_PAGE_VALID| _CACHE_CACHABLE_COW) >> 6)

	or	t0, t0, t1

	mtc0	t0, CP0_ENTRYLO0	# physaddr, VG, cach exlwr

	li	t0, ((_PAGE_GLOBAL|_PAGE_VALID| _PAGE_DIRTY|_CACHE_CACHABLE_COW) >> 6)

	or	t0, t0, t2

	mtc0	t0, CP0_ENTRYLO1	# physaddr, DVG, cach exlwr

	li	t0, 0x1ffe000		# MAPPED_KERN_TLBMASK, TLBPGMASK_16M

	mtc0	t0, CP0_PAGEMASK

	li	t0, 0			# KMAP_INX

	mtc0	t0, CP0_INDEX

	li	t0, 1

	mtc0	t0, CP0_WIRED

	tlbwi

#else

	mtc0	zero, CP0_WIRED

#endif

	.endm



/*

 * Intentionally empty macro, used in head.S. Override in

 * arch/mips/mach-xxx/kernel-entry-init.h when necessary.

arch/mips/kernel/head.S

+0 −39
Original line number Diff line number Diff line
@@ -27,45 +27,6 @@ 


#include <kernel-entry-init.h>



	/*

	 * inputs are the text nasid in t1, data nasid in t2.

	 */

	.macro MAPPED_KERNEL_SETUP_TLB

#ifdef CONFIG_MAPPED_KERNEL

	/*

	 * This needs to read the nasid - assume 0 for now.

	 * Drop in 0xffffffffc0000000 in tlbhi, 0+VG in tlblo_0,

	 * 0+DVG in tlblo_1.

	 */

	dli	t0, 0xffffffffc0000000

	dmtc0	t0, CP0_ENTRYHI

	li	t0, 0x1c000		# Offset of text into node memory

	dsll	t1, NASID_SHFT		# Shift text nasid into place

	dsll	t2, NASID_SHFT		# Same for data nasid

	or	t1, t1, t0		# Physical load address of kernel text

	or	t2, t2, t0		# Physical load address of kernel data

	dsrl	t1, 12			# 4K pfn

	dsrl	t2, 12			# 4K pfn

	dsll	t1, 6			# Get pfn into place

	dsll	t2, 6			# Get pfn into place

	li	t0, ((_PAGE_GLOBAL|_PAGE_VALID| _CACHE_CACHABLE_COW) >> 6)

	or	t0, t0, t1

	mtc0	t0, CP0_ENTRYLO0	# physaddr, VG, cach exlwr

	li	t0, ((_PAGE_GLOBAL|_PAGE_VALID| _PAGE_DIRTY|_CACHE_CACHABLE_COW) >> 6)

	or	t0, t0, t2

	mtc0	t0, CP0_ENTRYLO1	# physaddr, DVG, cach exlwr

	li	t0, 0x1ffe000		# MAPPED_KERN_TLBMASK, TLBPGMASK_16M

	mtc0	t0, CP0_PAGEMASK

	li	t0, 0			# KMAP_INX

	mtc0	t0, CP0_INDEX

	li	t0, 1

	mtc0	t0, CP0_WIRED

	tlbwi

#else

	mtc0	zero, CP0_WIRED

#endif

	.endm



	/*

	 * For the moment disable interrupts, mark the kernel mode and

	 * set ST0_KX so that the CPU does not spit fire when using