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Commit 23107c54 authored by Catalin Marinas's avatar Catalin Marinas Committed by Russell King
Browse files

ARM: 5995/1: ARM: Add L2x0 outer_sync() support (3/4) 



The L2x0 cache controllers need to explicitly drain their write buffer
even for Normal Noncacheable memory accesses.

Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent 319f551a

arch/arm/mm/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -763,6 +763,7 @@ config CACHE_L2X0 
		   REALVIEW_EB_A9MP || ARCH_MX35 || ARCH_MX31 || MACH_REALVIEW_PBX || ARCH_NOMADIK || ARCH_OMAP4

	default y

	select OUTER_CACHE

	select OUTER_CACHE_SYNC

	help

	  This option enables the L2x0 PrimeCell.

arch/arm/mm/cache-l2x0.c

+10 −0
Original line number Diff line number Diff line
@@ -93,6 +93,15 @@ static inline void l2x0_flush_line(unsigned long addr) 
}

#endif



static void l2x0_cache_sync(void)

{

	unsigned long flags;



	spin_lock_irqsave(&l2x0_lock, flags);

	cache_sync();

	spin_unlock_irqrestore(&l2x0_lock, flags);

}



static inline void l2x0_inv_all(void)

{

	unsigned long flags;
@@ -225,6 +234,7 @@ void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask) 
	outer_cache.inv_range = l2x0_inv_range;

	outer_cache.clean_range = l2x0_clean_range;

	outer_cache.flush_range = l2x0_flush_range;

	outer_cache.sync = l2x0_cache_sync;



	printk(KERN_INFO "L2X0 cache controller enabled\n");

}