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Commit 22e02c0b authored by Ville Syrjälä's avatar Ville Syrjälä Committed by Daniel Vetter
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drm/i915: Add missing POSTING_READ()s to BXT dbuf enable sequence 



Do a POSTING_READ() between the DBUF_CTL register write and the
udelay() to make sure we really wait after the register write has
happened.

Spotted while reviewing Damien's SKL cdclk patch which had the
POSTING_READ()s.

Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: default avatarImre Deak <imre.deak@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 813b5e69

drivers/gpu/drm/i915/intel_display.c

+4 −0
Original line number Original line Diff line number Diff line
@@ -5482,6 +5482,8 @@ void broxton_init_cdclk(struct drm_device *dev) 
	broxton_set_cdclk(dev, 624000);

	broxton_set_cdclk(dev, 624000);





	I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);

	I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);

	POSTING_READ(DBUF_CTL);



	udelay(10);

	udelay(10);





	if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))

	if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
@@ -5493,6 +5495,8 @@ void broxton_uninit_cdclk(struct drm_device *dev) 
	struct drm_i915_private *dev_priv = dev->dev_private;

	struct drm_i915_private *dev_priv = dev->dev_private;





	I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);

	I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);

	POSTING_READ(DBUF_CTL);



	udelay(10);

	udelay(10);





	if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)

	if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)