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Commit 22bd1f7e authored by Stephen Warren's avatar Stephen Warren
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ARM: dt: tegra seaboard: fix I2C2 SCL rate 



This I2C bus is used for EDID/DDC reads and other "slow" I2C devices.
This requires a 100KHz SCL (clock) rate.

Signed-off-by: default avatarStephen Warren <swarren@nvidia.com>
parent b46b0b54

arch/arm/boot/dts/tegra-seaboard.dts

+1 −1
Original line number Diff line number Diff line
@@ -281,7 +281,7 @@ 
	};



	i2c@7000c400 {

		clock-frequency = <400000>;

		clock-frequency = <100000>;

	};



	i2c@7000c500 {