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Commit 22b196a5 authored by Shefali Jain's avatar Shefali Jain Committed by Taniya Das
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Documentation: bindings: Update documentation for npucc for LITO 



Add Network Processing driver in documentation for lito.

Change-Id: I9fc82af3f19c234f9f258f005d7f8243bc72f195
Signed-off-by: default avatarShefali Jain <shefjain@codeaurora.org>
parent 82701729

Documentation/devicetree/bindings/clock/qcom,npucc.txt

+2 −1
Original line number Diff line number Diff line
@@ -2,7 +2,8 @@ Qualcomm Technologies, Inc. NPU Clock & Reset Controller Bindings 
-----------------------------------------------------------------



Required properties :

- compatible:		Should be "qcom,npucc-kona".

- compatible:		Should be "qcom,npucc-kona"

				  "qcom,lito-npucc".

- reg:			Shall contain base register addresses and sizes.

- reg-names:		Names of the register bases listed in the same order as

			in the reg property.  Shall include: "cc", "qdsp6ss",

include/dt-bindings/clock/qcom,npucc-lito.h

+38 −43
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0-only */

/* Copyright (c) 2018, The Linux Foundation. All rights reserved. */

/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. */



#ifndef _DT_BINDINGS_CLK_QCOM_NPU_CC_LITO_H

#define _DT_BINDINGS_CLK_QCOM_NPU_CC_LITO_H
@@ -8,51 +8,46 @@ 
#define NPU_CC_PLL0_OUT_EVEN					1

#define NPU_CC_PLL1						2

#define NPU_CC_PLL1_OUT_EVEN					3

#define NPU_Q6SS_PLL						4

#define NPU_CC_CAL_HM0_CLK					5

#define NPU_CC_CAL_HM0_CLK_SRC					6

#define NPU_CC_CAL_HM0_DPM_IP_CLK				7

#define NPU_CC_CAL_HM0_PERF_CNT_CLK				8

#define NPU_CC_CAL_HM1_CDC_CLK					9

#define NPU_CC_CAL_HM1_CLK					10

#define NPU_CC_CAL_HM1_CLK_SRC					11

#define NPU_CC_CAL_HM1_DPM_IP_CLK				12

#define NPU_CC_CAL_HM1_PERF_CNT_CLK				13

#define NPU_CC_CORE_CLK						14

#define NPU_CC_CORE_CLK_SRC					15

#define NPU_CC_DL_DPM_CLK					16

#define NPU_CC_DL_LLM_CLK					17

#define NPU_CC_DPM_CLK						18

#define NPU_CC_DPM_TEMP_CLK					19

#define NPU_CC_DPM_XO_CLK					20

#define NPU_CC_DSP_AHBM_CLK					21

#define NPU_CC_DSP_AHBS_CLK					22

#define NPU_CC_DSP_AXI_CLK					23

#define NPU_CC_DSP_BWMON_AHB_CLK				24

#define NPU_CC_DSP_BWMON_CLK					25

#define NPU_CC_ISENSE_CLK					26

#define NPU_CC_LLM_CLK						27

#define NPU_CC_LLM_CURR_CLK					28

#define NPU_CC_LLM_TEMP_CLK					29

#define NPU_CC_LLM_XO_CLK					30

#define NPU_CC_LMH_CLK_SRC					31

#define NPU_CC_NOC_AHB_CLK					32

#define NPU_CC_NOC_AXI_CLK					33

#define NPU_CC_NOC_DMA_CLK					34

#define NPU_CC_AON_CLK						35

#define NPU_CC_ATB_CLK						36

#define NPU_CC_BTO_CORE_CLK					37

#define NPU_CC_BWMON_CLK					38

#define NPU_CC_RSC_XO_CLK					39

#define NPU_CC_S2P_CLK						40

#define NPU_CC_XO_CLK						41

#define NPU_CC_XO_CLK_SRC					42

#define NPU_DSP_CORE_CLK_SRC					43

#define NPU_CC_CAL_HM0_CDC_CLK					44

#define NPU_CC_CAL_HM0_CLK					4

#define NPU_CC_CAL_HM0_CLK_SRC					5

#define NPU_CC_CAL_HM0_DPM_IP_CLK				6

#define NPU_CC_CAL_HM0_PERF_CNT_CLK				7

#define NPU_CC_CAL_HM0_CDC_CLK					8

#define NPU_CC_CORE_CLK						9

#define NPU_CC_CORE_CLK_SRC					10

#define NPU_CC_DL_DPM_CLK					11

#define NPU_CC_DL_LLM_CLK					12

#define NPU_CC_DPM_CLK						13

#define NPU_CC_DPM_TEMP_CLK					14

#define NPU_CC_DPM_XO_CLK					15

#define NPU_CC_DSP_AHBM_CLK					16

#define NPU_CC_DSP_AHBS_CLK					17

#define NPU_CC_DSP_AXI_CLK					18

#define NPU_CC_DSP_BWMON_AHB_CLK				19

#define NPU_CC_DSP_BWMON_CLK					20

#define NPU_CC_ISENSE_CLK					21

#define NPU_CC_LLM_CLK						22

#define NPU_CC_LLM_CURR_CLK					23

#define NPU_CC_LLM_TEMP_CLK					24

#define NPU_CC_LLM_XO_CLK					25

#define NPU_CC_LMH_CLK_SRC					26

#define NPU_CC_NOC_AHB_CLK					27

#define NPU_CC_NOC_AXI_CLK					28

#define NPU_CC_NOC_DMA_CLK					29

#define NPU_CC_BTO_CORE_CLK					30

#define NPU_CC_BWMON_CLK					31

#define NPU_CC_RSC_XO_CLK					32

#define NPU_CC_S2P_CLK						33

#define NPU_CC_XO_CLK						34

#define NPU_CC_XO_CLK_SRC					35

#define NPU_DSP_CORE_CLK_SRC					36

#define NPU_Q6SS_PLL						37



#define NPU_CC_CAL_HM0_BCR					0

#define NPU_CC_CAL_HM1_BCR					1

#define NPU_CC_CORE_BCR						2

#define NPU_CC_DSP_BCR						3



#define NPU_CC_DPM_TEMP_CLK_ARES				4

#define NPU_CC_LLM_TEMP_CLK_ARES				5

#define NPU_CC_LLM_CURR_CLK_ARES				6

#endif