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Commit 227c95d9 authored by Ben Skeggs's avatar Ben Skeggs
Browse files

drm/nouveau/gr: directly use instmem where currently possible 



Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent 358ce601

drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c

+15 −12
Original line number Diff line number Diff line
@@ -1272,34 +1272,37 @@ gf100_grctx_generate(struct gf100_gr *gr) 
	struct gf100_grctx_oclass *oclass = (void *)nv_engine(gr)->cclass;

	struct nvkm_subdev *subdev = &gr->base.engine.subdev;

	struct nvkm_device *device = subdev->device;

	struct nvkm_gpuobj *chan;

	struct nvkm_memory *chan;

	struct gf100_grctx info;

	int ret, i;

	u64 addr;



	/* allocate memory to for a "channel", which we'll use to generate

	 * the default context values

	 */

	ret = nvkm_gpuobj_new(nv_object(gr), NULL, 0x80000 + gr->size,

			      0x1000, NVOBJ_FLAG_ZERO_ALLOC, &chan);

	ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 0x80000 + gr->size,

			      0x1000, true, &chan);

	if (ret) {

		nvkm_error(subdev, "failed to allocate chan memory, %d\n", ret);

		return ret;

	}



	addr = nvkm_memory_addr(chan);



	/* PGD pointer */

	nvkm_kmap(chan);

	nvkm_wo32(chan, 0x0200, lower_32_bits(chan->addr + 0x1000));

	nvkm_wo32(chan, 0x0204, upper_32_bits(chan->addr + 0x1000));

	nvkm_wo32(chan, 0x0200, lower_32_bits(addr + 0x1000));

	nvkm_wo32(chan, 0x0204, upper_32_bits(addr + 0x1000));

	nvkm_wo32(chan, 0x0208, 0xffffffff);

	nvkm_wo32(chan, 0x020c, 0x000000ff);



	/* PGT[0] pointer */

	nvkm_wo32(chan, 0x1000, 0x00000000);

	nvkm_wo32(chan, 0x1004, 0x00000001 | (chan->addr + 0x2000) >> 8);

	nvkm_wo32(chan, 0x1004, 0x00000001 | (addr + 0x2000) >> 8);



	/* identity-map the whole "channel" into its own vm */

	for (i = 0; i < chan->size / 4096; i++) {

		u64 addr = ((chan->addr + (i * 4096)) >> 8) | 1;

	for (i = 0; i < nvkm_memory_size(chan) / 4096; i++) {

		u64 addr = ((nvkm_memory_addr(chan) + (i * 4096)) >> 8) | 1;

		nvkm_wo32(chan, 0x2000 + (i * 8), lower_32_bits(addr));

		nvkm_wo32(chan, 0x2004 + (i * 8), upper_32_bits(addr));

	}
@@ -1309,7 +1312,7 @@ gf100_grctx_generate(struct gf100_gr *gr) 
	nvkm_wo32(chan, 0x0214, 0x00000000);

	nvkm_done(chan);



	nvkm_wr32(device, 0x100cb8, (chan->addr + 0x1000) >> 8);

	nvkm_wr32(device, 0x100cb8, (addr + 0x1000) >> 8);

	nvkm_wr32(device, 0x100cbc, 0x80000001);

	nvkm_msec(device, 2000,

		if (nvkm_rd32(device, 0x100c80) & 0x00008000)
@@ -1326,7 +1329,7 @@ gf100_grctx_generate(struct gf100_gr *gr) 
	/* make channel current */

	if (gr->firmware) {

		nvkm_wr32(device, 0x409840, 0x00000030);

		nvkm_wr32(device, 0x409500, 0x80000000 | chan->addr >> 12);

		nvkm_wr32(device, 0x409500, 0x80000000 | addr >> 12);

		nvkm_wr32(device, 0x409504, 0x00000003);

		nvkm_msec(device, 2000,

			if (nvkm_rd32(device, 0x409800) & 0x00000010)
@@ -1341,7 +1344,7 @@ gf100_grctx_generate(struct gf100_gr *gr) 
		nvkm_done(chan);

	} else {

		nvkm_wr32(device, 0x409840, 0x80000000);

		nvkm_wr32(device, 0x409500, 0x80000000 | chan->addr >> 12);

		nvkm_wr32(device, 0x409500, 0x80000000 | addr >> 12);

		nvkm_wr32(device, 0x409504, 0x00000001);

		nvkm_msec(device, 2000,

			if (nvkm_rd32(device, 0x409800) & 0x80000000)
@@ -1376,7 +1379,7 @@ gf100_grctx_generate(struct gf100_gr *gr) 
	}



done:

	nvkm_gpuobj_ref(NULL, &chan);

	nvkm_memory_del(&chan);

	return ret;

}

drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c

+29 −19
Original line number Diff line number Diff line
@@ -283,6 +283,7 @@ gf100_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 
	struct gf100_gr_data *data = gr->mmio_data;

	struct gf100_gr_mmio *mmio = gr->mmio_list;

	struct gf100_gr_chan *chan;

	struct nvkm_device *device = gr->base.engine.subdev.device;

	struct nvkm_gpuobj *image;

	int ret, i;
@@ -298,29 +299,32 @@ gf100_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 
	 * fuc to modify some per-context register settings on first load

	 * of the context.

	 */

	ret = nvkm_gpuobj_new(nv_object(chan), NULL, 0x1000, 0x100, 0,

			      &chan->mmio);

	ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 0x1000, 0x100,

			      false, &chan->mmio);

	if (ret)

		return ret;



	ret = nvkm_gpuobj_map_vm(nv_gpuobj(chan->mmio), vm,

				 NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS,

				 &chan->mmio_vma);

	ret = nvkm_vm_get(vm, 0x1000, 12, NV_MEM_ACCESS_RW |

			  NV_MEM_ACCESS_SYS, &chan->mmio_vma);

	if (ret)

		return ret;



	nvkm_memory_map(chan->mmio, &chan->mmio_vma, 0);



	/* allocate buffers referenced by mmio list */

	for (i = 0; data->size && i < ARRAY_SIZE(gr->mmio_data); i++) {

		ret = nvkm_gpuobj_new(nv_object(chan), NULL, data->size,

				      data->align, 0, &chan->data[i].mem);

		ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST,

				      data->size, data->align, false,

				      &chan->data[i].mem);

		if (ret)

			return ret;



		ret = nvkm_gpuobj_map_vm(chan->data[i].mem, vm, data->access,

					 &chan->data[i].vma);

		ret = nvkm_vm_get(vm, nvkm_memory_size(chan->data[i].mem),

				  12, data->access, &chan->data[i].vma);

		if (ret)

			return ret;



		nvkm_memory_map(chan->data[i].mem, &chan->data[i].vma, 0);

		data++;

	}
@@ -372,12 +376,18 @@ gf100_gr_context_dtor(struct nvkm_object *object) 
	int i;



	for (i = 0; i < ARRAY_SIZE(chan->data); i++) {

		nvkm_gpuobj_unmap(&chan->data[i].vma);

		nvkm_gpuobj_ref(NULL, &chan->data[i].mem);

		if (chan->data[i].vma.node) {

			nvkm_vm_unmap(&chan->data[i].vma);

			nvkm_vm_put(&chan->data[i].vma);

		}

		nvkm_memory_del(&chan->data[i].mem);

	}



	nvkm_gpuobj_unmap(&chan->mmio_vma);

	nvkm_gpuobj_ref(NULL, &chan->mmio);

	if (chan->mmio_vma.node) {

		nvkm_vm_unmap(&chan->mmio_vma);

		nvkm_vm_put(&chan->mmio_vma);

	}

	nvkm_memory_del(&chan->mmio);



	nvkm_gr_context_destroy(&chan->base);

}
@@ -1490,8 +1500,8 @@ gf100_gr_init(struct nvkm_object *object) 
	nvkm_wr32(device, GPC_BCAST(0x088c), 0x00000000);

	nvkm_wr32(device, GPC_BCAST(0x0890), 0x00000000);

	nvkm_wr32(device, GPC_BCAST(0x0894), 0x00000000);

	nvkm_wr32(device, GPC_BCAST(0x08b4), gr->unk4188b4->addr >> 8);

	nvkm_wr32(device, GPC_BCAST(0x08b8), gr->unk4188b8->addr >> 8);

	nvkm_wr32(device, GPC_BCAST(0x08b4), nvkm_memory_addr(gr->unk4188b4) >> 8);

	nvkm_wr32(device, GPC_BCAST(0x08b8), nvkm_memory_addr(gr->unk4188b8) >> 8);



	gf100_gr_mmio(gr, oclass->mmio);
@@ -1634,8 +1644,8 @@ gf100_gr_dtor(struct nvkm_object *object) 
	gf100_gr_dtor_fw(&gr->fuc41ac);

	gf100_gr_dtor_fw(&gr->fuc41ad);



	nvkm_gpuobj_ref(NULL, &gr->unk4188b8);

	nvkm_gpuobj_ref(NULL, &gr->unk4188b4);

	nvkm_memory_del(&gr->unk4188b8);

	nvkm_memory_del(&gr->unk4188b4);



	nvkm_gr_destroy(&gr->base);

}
@@ -1675,12 +1685,12 @@ gf100_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 
		gr->firmware = true;

	}



	ret = nvkm_gpuobj_new(nv_object(gr), NULL, 0x1000, 256, 0,

	ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 0x1000, 256, false,

			      &gr->unk4188b4);

	if (ret)

		return ret;



	ret = nvkm_gpuobj_new(nv_object(gr), NULL, 0x1000, 256, 0,

	ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 0x1000, 256, false,

			      &gr->unk4188b8);

	if (ret)

		return ret;

drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h

+4 −4
Original line number Diff line number Diff line
@@ -95,8 +95,8 @@ struct gf100_gr { 
	u8 ppc_nr[GPC_MAX];

	u8 ppc_tpc_nr[GPC_MAX][4];



	struct nvkm_gpuobj *unk4188b4;

	struct nvkm_gpuobj *unk4188b8;

	struct nvkm_memory *unk4188b4;

	struct nvkm_memory *unk4188b8;



	struct gf100_gr_data mmio_data[4];

	struct gf100_gr_mmio mmio_list[4096/8];
@@ -109,11 +109,11 @@ struct gf100_gr { 
struct gf100_gr_chan {

	struct nvkm_gr_chan base;



	struct nvkm_gpuobj *mmio;

	struct nvkm_memory *mmio;

	struct nvkm_vma mmio_vma;

	int mmio_nr;

	struct {

		struct nvkm_gpuobj *mem;

		struct nvkm_memory *mem;

		struct nvkm_vma vma;

	} data[4];

};

drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c

+2 −2
Original line number Diff line number Diff line
@@ -218,8 +218,8 @@ gk104_gr_init(struct nvkm_object *object) 
	nvkm_wr32(device, GPC_BCAST(0x088c), 0x00000000);

	nvkm_wr32(device, GPC_BCAST(0x0890), 0x00000000);

	nvkm_wr32(device, GPC_BCAST(0x0894), 0x00000000);

	nvkm_wr32(device, GPC_BCAST(0x08b4), gr->unk4188b4->addr >> 8);

	nvkm_wr32(device, GPC_BCAST(0x08b8), gr->unk4188b8->addr >> 8);

	nvkm_wr32(device, GPC_BCAST(0x08b4), nvkm_memory_addr(gr->unk4188b4) >> 8);

	nvkm_wr32(device, GPC_BCAST(0x08b8), nvkm_memory_addr(gr->unk4188b8) >> 8);



	gf100_gr_mmio(gr, oclass->mmio);

drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c

+2 −2
Original line number Diff line number Diff line
@@ -280,8 +280,8 @@ gk20a_gr_init(struct nvkm_object *object) 
		return ret;



	/* MMU debug buffer */

	nvkm_wr32(device, 0x100cc8, gr->unk4188b4->addr >> 8);

	nvkm_wr32(device, 0x100ccc, gr->unk4188b8->addr >> 8);

	nvkm_wr32(device, 0x100cc8, nvkm_memory_addr(gr->unk4188b4) >> 8);

	nvkm_wr32(device, 0x100ccc, nvkm_memory_addr(gr->unk4188b8) >> 8);



	if (oclass->init_gpc_mmu)

		oclass->init_gpc_mmu(gr);