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Commit 21f16289 authored by Dave Airlie's avatar Dave Airlie Committed by Linus Torvalds
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drm/i915: Fix i965 secured batchbuffer usage 



This 965G and above chipsets moved the batch buffer non-secure bits to
another place. This means that previous drm's allowed in-secure batchbuffers
to be submitted to the hardware from non-privileged users who are logged
into X and and have access to direct rendering.

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
Signed-off-by: default avatarLinus Torvalds <torvalds@linux-foundation.org>
parent d4ac2477

drivers/char/drm/i915_dma.c

+11 −3
Original line number Diff line number Diff line
@@ -184,6 +184,8 @@ static int i915_initialize(struct drm_device * dev, 
	 * private backbuffer/depthbuffer usage.

	 */

	dev_priv->use_mi_batchbuffer_start = 0;

	if (IS_I965G(dev)) /* 965 doesn't support older method */

		dev_priv->use_mi_batchbuffer_start = 1;



	/* Allow hardware batchbuffers unless told otherwise.

	 */
@@ -517,8 +519,13 @@ static int i915_dispatch_batchbuffer(struct drm_device * dev, 


		if (dev_priv->use_mi_batchbuffer_start) {

			BEGIN_LP_RING(2);

			if (IS_I965G(dev)) {

				OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);

				OUT_RING(batch->start);

			} else {

				OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));

				OUT_RING(batch->start | MI_BATCH_NON_SECURE);

			}

			ADVANCE_LP_RING();

		} else {

			BEGIN_LP_RING(4);
@@ -735,6 +742,7 @@ static int i915_setparam(DRM_IOCTL_ARGS) 


	switch (param.param) {

	case I915_SETPARAM_USE_MI_BATCHBUFFER_START:

		if (!IS_I965G(dev))

			dev_priv->use_mi_batchbuffer_start = param.value;

		break;

	case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:

drivers/char/drm/i915_drv.h

+1 −0
Original line number Diff line number Diff line
@@ -282,6 +282,7 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller); 
#define MI_BATCH_BUFFER_START 	(0x31<<23)

#define MI_BATCH_BUFFER_END 	(0xA<<23)

#define MI_BATCH_NON_SECURE	(1)

#define MI_BATCH_NON_SECURE_I965 (1<<8)



#define MI_WAIT_FOR_EVENT       ((0x3<<23))

#define MI_WAIT_FOR_PLANE_A_FLIP      (1<<2)