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Commit 218dc618 authored by Kavya Nunna's avatar Kavya Nunna
Browse files

power: smblite-lib: Force 5V on OTG enable 



Add register write when OTG cable is detected to
ensure to override the adaptive voltage negotiation
algorithm and ensure boost VOUT will be 5V for OTG.

Change-Id: I6c143b31f095ebad92e58d1cd3c9ab3e872a2241
Signed-off-by: default avatarKavya Nunna <knunna@codeaurora.org>
parent 757f1d14

drivers/power/supply/qcom/smblite-lib.c

+8 −1
Original line number Original line Diff line number Diff line
@@ -191,6 +191,7 @@ static void smblite_lib_notify_device_mode(struct smb_charger *chg, bool enable) 
	extcon_set_state_sync(chg->extcon, EXTCON_USB, enable);

	extcon_set_state_sync(chg->extcon, EXTCON_USB, enable);

}

}





#define VBOOST_5P00V	0x03

static void smblite_lib_notify_usb_host(struct smb_charger *chg, bool enable)

static void smblite_lib_notify_usb_host(struct smb_charger *chg, bool enable)

{

{

	int rc = 0;

	int rc = 0;
@@ -208,7 +209,13 @@ static void smblite_lib_notify_usb_host(struct smb_charger *chg, bool enable) 
				"Couldn't enable VBUS in OTG mode rc=%d\n", rc);

				"Couldn't enable VBUS in OTG mode rc=%d\n", rc);

			return;

			return;

		}

		}



		rc = smblite_lib_masked_write(chg, DCDC_BST_VREG_SEL,

					VBOOST_MASK, VBOOST_5P00V);

		if (rc < 0) {

			smblite_lib_err(chg,

				"Couldn't write BST_VREG_SEL rc=%d\n", rc);

			return;

		}

		smblite_lib_notify_extcon_props(chg, EXTCON_USB_HOST);

		smblite_lib_notify_extcon_props(chg, EXTCON_USB_HOST);

	} else {

	} else {

		smblite_lib_dbg(chg, PR_OTG, "disabling VBUS in OTG mode\n");

		smblite_lib_dbg(chg, PR_OTG, "disabling VBUS in OTG mode\n");

drivers/power/supply/qcom/smblite-reg.h

+3 −0
Original line number Original line Diff line number Diff line
@@ -101,6 +101,9 @@ enum { 
#define DCDC_CMD_OTG_REG			(DCDC_BASE + 0x50)

#define DCDC_CMD_OTG_REG			(DCDC_BASE + 0x50)

#define OTG_EN_BIT				BIT(0)

#define OTG_EN_BIT				BIT(0)





#define DCDC_BST_VREG_SEL			(DCDC_BASE + 0x52)

#define VBOOST_MASK				GENMASK(1, 0)



#define DCDC_OTG_CFG_REG			(DCDC_BASE + 0x56)

#define DCDC_OTG_CFG_REG			(DCDC_BASE + 0x56)

#define OTG_EN_SRC_CFG_BIT			BIT(0)

#define OTG_EN_SRC_CFG_BIT			BIT(0)