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Commit 216ac529 authored by Romain Perier's avatar Romain Perier Committed by Heiko Stuebner
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clk: rockchip: export clock pclk_efuse_256 for RK3368 SoCs 



This exports the clock for the pclk gate of the eFuse that is part of
the RK3368 SoCs. So we can use it from the dt-bindings.

Signed-off-by: default avatarRomain Perier <romain.perier@collabora.com>
Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
parent 51cec870

drivers/clk/rockchip/clk-rk3368.c

+1 −1
Original line number Diff line number Diff line
@@ -711,7 +711,7 @@ static struct rockchip_clk_branch rk3368_clk_branches[] __initdata = { 
	GATE(PCLK_SIM, "pclk_sim", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 8, GFLAGS),

	GATE(PCLK_PWM1, "pclk_pwm1", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 6, GFLAGS),

	GATE(PCLK_UART2, "pclk_uart2", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 5, GFLAGS),

	GATE(0, "pclk_efuse_256", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 1, GFLAGS),

	GATE(PCLK_EFUSE256, "pclk_efuse_256", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 1, GFLAGS),

	GATE(0, "pclk_efuse_1024", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 0, GFLAGS),



	/*