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Commit 2169f9e9 authored by Vipin Deep Kaur's avatar Vipin Deep Kaur Committed by Gerrit - the friendly Code Review server
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gpi: Evaluate EE GSI registers offset for QUP 



The GSI EE registers offset may vary for some targets based
on the GSI HW version. If so, read the variable offset for
these registers from dt node property.

Change-Id: I585d56552eddc5e6343ebacdc8c004a2f7303d4e
Signed-off-by: default avatarVipin Deep Kaur <vkaur@codeaurora.org>
parent ca4c8252

drivers/dma/qcom/gpi.c

+20 −32
Original line number Diff line number Diff line
@@ -434,6 +434,7 @@ struct gpi_dev { 
	struct device *dev;

	struct resource *res;

	void __iomem *regs;

	void *ee_base; /*ee register base address*/

	u32 max_gpii; /* maximum # of gpii instances available per gpi block */

	u32 gpii_mask; /* gpii instances available for apps */

	u32 ev_factor; /* ev ring length factor */
@@ -524,8 +525,6 @@ static irqreturn_t gpi_handle_irq(int irq, void *data); 
static void gpi_ring_recycle_ev_element(struct gpi_ring *ring);

static int gpi_ring_add_element(struct gpi_ring *ring, void **wp);

static void gpi_process_events(struct gpii *gpii);

static u64 get_gpi_ee_base(u64 base, int num_gpii);





static inline struct gpii_chan *to_gpii_chan(struct dma_chan *dma_chan)

{
@@ -2640,24 +2639,12 @@ static int gpi_smmu_init(struct gpi_dev *gpi_dev) 
	return ret;

}



/* Variabe EE register offset Kona */

static u64 get_gpi_ee_base(u64 base, int num_gpii)

{

	if (num_gpii == QUP0_NUM_GPII_KONA)

		base -= QUP0_VAR_OFFSET_KONA;

	else

		base -= QUP1_VAR_OFFSET_KONA;

	return base;

}



static int gpi_probe(struct platform_device *pdev)

{

	struct gpi_dev *gpi_dev;

	int ret, i;

	const char *mode = NULL;

	u64 ee_base;

	u64 base;

	bool gpii_offset;

	u32 gpi_ee_offset;



	gpi_dev = devm_kzalloc(&pdev->dev, sizeof(*gpi_dev), GFP_KERNEL);

	if (!gpi_dev)
@@ -2678,6 +2665,8 @@ static int gpi_probe(struct platform_device *pdev) 
		return -EFAULT;

	}



	gpi_dev->ee_base = gpi_dev->regs;



	ret = of_property_read_u32(gpi_dev->dev->of_node, "qcom,max-num-gpii",

				   &gpi_dev->max_gpii);

	if (ret) {
@@ -2692,8 +2681,13 @@ static int gpi_probe(struct platform_device *pdev) 
		return ret;

	}



	gpii_offset = of_property_read_bool(gpi_dev->dev->of_node,

						"qcom,gpii_offset");

	ret = of_property_read_u32(gpi_dev->dev->of_node,

					"qcom,gpi-ee-offset", &gpi_ee_offset);

	if (ret)

		GPI_LOG(gpi_dev, "No variable ee offset present\n");

	else

		gpi_dev->ee_base =

		(void *)((u64)gpi_dev->ee_base - gpi_ee_offset);



	ret = of_property_read_u32(gpi_dev->dev->of_node, "qcom,ev-factor",

				   &gpi_dev->ev_factor);
@@ -2760,12 +2754,6 @@ static int gpi_probe(struct platform_device *pdev) 
	if (!gpi_dev->gpiis)

		return -ENOMEM;



	if (gpii_offset) {

		base = (u64)gpi_dev->regs;

		ee_base = get_gpi_ee_base(base, gpi_dev->max_gpii);

	} else

		ee_base = (u64)gpi_dev->regs;



	/* setup all the supported gpii */

	INIT_LIST_HEAD(&gpi_dev->dma_device.channels);

	for (i = 0; i < gpi_dev->max_gpii; i++) {
@@ -2776,9 +2764,9 @@ static int gpi_probe(struct platform_device *pdev) 
			continue;



		/* set up ev cntxt register map */

		gpii->ev_cntxt_base_reg = (void *)ee_base +

		gpii->ev_cntxt_base_reg = gpi_dev->ee_base +

			GPI_GPII_n_EV_CH_k_CNTXT_0_OFFS(i, 0);

		gpii->ev_cntxt_db_reg = (void *)ee_base +

		gpii->ev_cntxt_db_reg = gpi_dev->ee_base +

			GPI_GPII_n_EV_CH_k_DOORBELL_0_OFFS(i, 0);

		gpii->ev_ring_base_lsb_reg = gpii->ev_cntxt_base_reg +

			CNTXT_2_RING_BASE_LSB;
@@ -2786,11 +2774,11 @@ static int gpi_probe(struct platform_device *pdev) 
			CNTXT_4_RING_RP_LSB;

		gpii->ev_ring_wp_lsb_reg = gpii->ev_cntxt_base_reg +

			CNTXT_6_RING_WP_LSB;

		gpii->ev_cmd_reg = (void *)ee_base +

		gpii->ev_cmd_reg = gpi_dev->ee_base +

			GPI_GPII_n_EV_CH_CMD_OFFS(i);

		gpii->ieob_src_reg = (void *)ee_base +

		gpii->ieob_src_reg = gpi_dev->ee_base +

			GPI_GPII_n_CNTXT_SRC_IEOB_IRQ_OFFS(i);

		gpii->ieob_clr_reg = (void *)ee_base +

		gpii->ieob_clr_reg = gpi_dev->ee_base +

			GPI_GPII_n_CNTXT_SRC_IEOB_IRQ_CLR_OFFS(i);



		/* set up irq */
@@ -2807,9 +2795,9 @@ static int gpi_probe(struct platform_device *pdev) 
			struct gpii_chan *gpii_chan = &gpii->gpii_chan[chan];



			/* set up ch cntxt register map */

			gpii_chan->ch_cntxt_base_reg = (void *)ee_base +

			gpii_chan->ch_cntxt_base_reg = gpi_dev->ee_base +

				GPI_GPII_n_CH_k_CNTXT_0_OFFS(i, chan);

			gpii_chan->ch_cntxt_db_reg = (void *)ee_base +

			gpii_chan->ch_cntxt_db_reg = gpi_dev->ee_base +

				GPI_GPII_n_CH_k_DOORBELL_0_OFFS(i, chan);

			gpii_chan->ch_ring_base_lsb_reg =

				gpii_chan->ch_cntxt_base_reg +
@@ -2820,7 +2808,7 @@ static int gpi_probe(struct platform_device *pdev) 
			gpii_chan->ch_ring_wp_lsb_reg =

				gpii_chan->ch_cntxt_base_reg +

				CNTXT_6_RING_WP_LSB;

			gpii_chan->ch_cmd_reg = (void *)ee_base +

			gpii_chan->ch_cmd_reg = gpi_dev->ee_base +

				GPI_GPII_n_CH_CMD_OFFS(i);



			/* vchan setup */
@@ -2836,7 +2824,7 @@ static int gpi_probe(struct platform_device *pdev) 
			     (unsigned long)gpii);

		init_completion(&gpii->cmd_completion);

		gpii->gpii_id = i;

		gpii->regs = (void *)ee_base;

		gpii->regs = gpi_dev->ee_base;

		gpii->gpi_dev = gpi_dev;

		atomic_set(&gpii->dbg_index, 0);

	}

drivers/dma/qcom/msm_gpi_mmio.h

+0 −4
Original line number Diff line number Diff line
@@ -216,7 +216,3 @@ enum CNTXT_OFFS { 
#define GPI_GPII_n_CH_k_SCRATCH_3_OFFS(n, k) \

	(0x2006C + (0x4000 * (n)) + (0x80 * (k)))

/* Variabe EE register offset */

#define QUP0_NUM_GPII_KONA 15

#define QUP0_VAR_OFFSET_KONA (0x1000)

#define QUP1_VAR_OFFSET_KONA (0x6000)