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Commit 215ed200 authored by John Crispin's avatar John Crispin Committed by Ralf Baechle
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MIPS: lantiq: add xway soc ids 



Add the soc ids for additional xway socs. The patch also merges the amazon_se
code with the other socs.

Signed-off-by: default avatarJohn Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/3707/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 730fa039

arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h

+21 −6
Original line number Diff line number Diff line
@@ -17,17 +17,32 @@ 
#define SOC_ID_DANUBE1		0x129

#define SOC_ID_DANUBE2		0x12B

#define SOC_ID_TWINPASS		0x12D

#define SOC_ID_AMAZON_SE	0x152

#define SOC_ID_AMAZON_SE_1	0x152 /* 50601 */

#define SOC_ID_AMAZON_SE_2	0x153 /* 50600 */

#define SOC_ID_ARX188		0x16C

#define SOC_ID_ARX168		0x16D

#define SOC_ID_ARX168_1		0x16D

#define SOC_ID_ARX168_2		0x16E

#define SOC_ID_ARX182		0x16F

#define SOC_ID_GRX188		0x170

#define SOC_ID_GRX168		0x171



#define SOC_ID_VRX288		0x1C0 /* v1.1 */

#define SOC_ID_VRX282		0x1C1 /* v1.1 */

#define SOC_ID_VRX268		0x1C2 /* v1.1 */

#define SOC_ID_GRX268		0x1C8 /* v1.1 */

#define SOC_ID_GRX288		0x1C9 /* v1.1 */

#define SOC_ID_VRX288_2		0x00B /* v1.2 */

#define SOC_ID_VRX268_2		0x00C /* v1.2 */

#define SOC_ID_GRX288_2		0x00D /* v1.2 */

#define SOC_ID_GRX282_2		0x00E /* v1.2 */



 /* SoC Types */

#define SOC_TYPE_DANUBE		0x01

#define SOC_TYPE_TWINPASS	0x02

#define SOC_TYPE_AR9		0x03

#define SOC_TYPE_VR9		0x04

#define SOC_TYPE_AMAZON_SE	0x05

#define SOC_TYPE_VR9		0x04 /* v1.1 */

#define SOC_TYPE_VR9_2		0x05 /* v1.2 */

#define SOC_TYPE_AMAZON_SE	0x06



/* ASC0/1 - serial port */

#define LTQ_ASC0_BASE_ADDR	0x1E100400

arch/mips/lantiq/prom.h

+5 −0
Original line number Diff line number Diff line
@@ -10,16 +10,21 @@ 
#define _LTQ_PROM_H__



#define LTQ_SYS_TYPE_LEN	0x100

#define LTQ_SYS_REV_LEN         0x10



struct ltq_soc_info {

	unsigned char *name;

	unsigned int rev;

	unsigned char rev_type[LTQ_SYS_REV_LEN];

	unsigned int srev;

	unsigned int partnum;

	unsigned int type;

	unsigned char sys_type[LTQ_SYS_TYPE_LEN];

	unsigned char *compatible;

};



extern void ltq_soc_detect(struct ltq_soc_info *i);

extern void ltq_soc_setup(void);

extern void ltq_soc_init(void);



#endif

arch/mips/lantiq/xway/Makefile

+3 −3
Original line number Diff line number Diff line 
obj-y := pmu.o ebu.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o dma.o

obj-y := prom.o pmu.o ebu.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o dma.o



obj-$(CONFIG_SOC_XWAY) += clk-xway.o prom-xway.o setup-xway.o

obj-$(CONFIG_SOC_AMAZON_SE) += clk-ase.o prom-ase.o setup-ase.o

obj-$(CONFIG_SOC_XWAY) += clk-xway.o setup-xway.o

obj-$(CONFIG_SOC_AMAZON_SE) += clk-ase.o setup-ase.o



obj-$(CONFIG_LANTIQ_MACH_EASY50712) += mach-easy50712.o

obj-$(CONFIG_LANTIQ_MACH_EASY50601) += mach-easy50601.o

arch/mips/lantiq/xway/prom-ase.c

deleted100644 → 0
+0 −39
Original line number Diff line number Diff line 
/*

 *  This program is free software; you can redistribute it and/or modify it

 *  under the terms of the GNU General Public License version 2 as published

 *  by the Free Software Foundation.

 *

 *  Copyright (C) 2010 John Crispin <blogic@openwrt.org>

 */



#include <linux/export.h>

#include <linux/clk.h>

#include <asm/bootinfo.h>

#include <asm/time.h>



#include <lantiq_soc.h>



#include "../prom.h"



#define SOC_AMAZON_SE	"Amazon_SE"



#define PART_SHIFT	12

#define PART_MASK	0x0FFFFFFF

#define REV_SHIFT	28

#define REV_MASK	0xF0000000



void __init ltq_soc_detect(struct ltq_soc_info *i)

{

	i->partnum = (ltq_r32(LTQ_MPS_CHIPID) & PART_MASK) >> PART_SHIFT;

	i->rev = (ltq_r32(LTQ_MPS_CHIPID) & REV_MASK) >> REV_SHIFT;

	switch (i->partnum) {

	case SOC_ID_AMAZON_SE:

		i->name = SOC_AMAZON_SE;

		i->type = SOC_TYPE_AMAZON_SE;

		break;



	default:

		unreachable();

		break;

	}

}

arch/mips/lantiq/xway/prom-xway.c→arch/mips/lantiq/xway/prom.c

+115 −0
Original line number Diff line number Diff line
@@ -17,7 +17,17 @@ 


#define SOC_DANUBE	"Danube"

#define SOC_TWINPASS	"Twinpass"

#define SOC_AMAZON_SE	"Amazon_SE"

#define SOC_AR9		"AR9"

#define SOC_GR9		"GR9"

#define SOC_VR9		"VR9"



#define COMP_DANUBE	"lantiq,danube"

#define COMP_TWINPASS	"lantiq,twinpass"

#define COMP_AMAZON_SE	"lantiq,ase"

#define COMP_AR9	"lantiq,ar9"

#define COMP_GR9	"lantiq,gr9"

#define COMP_VR9	"lantiq,vr9"



#define PART_SHIFT	12

#define PART_MASK	0x0FFFFFFF
@@ -28,23 +38,74 @@ void __init ltq_soc_detect(struct ltq_soc_info *i) 
{

	i->partnum = (ltq_r32(LTQ_MPS_CHIPID) & PART_MASK) >> PART_SHIFT;

	i->rev = (ltq_r32(LTQ_MPS_CHIPID) & REV_MASK) >> REV_SHIFT;

	sprintf(i->rev_type, "1.%d", i->rev);

	switch (i->partnum) {

	case SOC_ID_DANUBE1:

	case SOC_ID_DANUBE2:

		i->name = SOC_DANUBE;

		i->type = SOC_TYPE_DANUBE;

		i->compatible = COMP_DANUBE;

		break;



	case SOC_ID_TWINPASS:

		i->name = SOC_TWINPASS;

		i->type = SOC_TYPE_DANUBE;

		i->compatible = COMP_TWINPASS;

		break;



	case SOC_ID_ARX188:

	case SOC_ID_ARX168:

	case SOC_ID_ARX168_1:

	case SOC_ID_ARX168_2:

	case SOC_ID_ARX182:

		i->name = SOC_AR9;

		i->type = SOC_TYPE_AR9;

		i->compatible = COMP_AR9;

		break;



	case SOC_ID_GRX188:

	case SOC_ID_GRX168:

		i->name = SOC_GR9;

		i->type = SOC_TYPE_AR9;

		i->compatible = COMP_GR9;

		break;



	case SOC_ID_AMAZON_SE_1:

	case SOC_ID_AMAZON_SE_2:

#ifdef CONFIG_PCI

		panic("ase is only supported for non pci kernels");

#endif

		i->name = SOC_AMAZON_SE;

		i->type = SOC_TYPE_AMAZON_SE;

		i->compatible = COMP_AMAZON_SE;

		break;



	case SOC_ID_VRX282:

	case SOC_ID_VRX268:

	case SOC_ID_VRX288:

		i->name = SOC_VR9;

		i->type = SOC_TYPE_VR9;

		i->compatible = COMP_VR9;

		break;



	case SOC_ID_GRX268:

	case SOC_ID_GRX288:

		i->name = SOC_GR9;

		i->type = SOC_TYPE_VR9;

		i->compatible = COMP_GR9;

		break;



	case SOC_ID_VRX268_2:

	case SOC_ID_VRX288_2:

		i->name = SOC_VR9;

		i->type = SOC_TYPE_VR9_2;

		i->compatible = COMP_VR9;

		break;



	case SOC_ID_GRX282_2:

	case SOC_ID_GRX288_2:

		i->name = SOC_GR9;

		i->type = SOC_TYPE_VR9_2;

		i->compatible = COMP_GR9;

		break;



	default: