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Commit 21240f9b authored by Alex Deucher's avatar Alex Deucher Committed by Dave Airlie
Browse files

drm/radeon/kms/atom: unify i2c gpio table handling 



Split the quirks and i2c_rec assignment into separate
functions used by both radeon_lookup_i2c_gpio() and
radeon_atombios_i2c_init().  This avoids duplicating code
and cases where quirks were only added to one of the
functions.

Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Cc: Jean Delvare <khali@linux-fr.org>
Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
parent d724502a

drivers/gpu/drm/radeon/radeon_atombios.c

+86 −128
Original line number Diff line number Diff line
@@ -62,29 +62,10 @@ union atom_supported_devices { 
	struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1;

};



static struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_device *rdev,

							       uint8_t id)

static void radeon_lookup_i2c_gpio_quirks(struct radeon_device *rdev,

					  ATOM_GPIO_I2C_ASSIGMENT *gpio,

					  u8 index)

{

	struct atom_context *ctx = rdev->mode_info.atom_context;

	ATOM_GPIO_I2C_ASSIGMENT *gpio;

	struct radeon_i2c_bus_rec i2c;

	int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);

	struct _ATOM_GPIO_I2C_INFO *i2c_info;

	uint16_t data_offset, size;

	int i, num_indices;



	memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));

	i2c.valid = false;



	if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {

		i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);



		num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /

			sizeof(ATOM_GPIO_I2C_ASSIGMENT);



		for (i = 0; i < num_indices; i++) {

			gpio = &i2c_info->asGPIO_Info[i];



	/* r4xx mask is technically not used by the hw, so patch in the legacy mask bits */

	if ((rdev->family == CHIP_R420) ||

	    (rdev->family == CHIP_R423) ||
@@ -99,7 +80,7 @@ static struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_device *rd 


	/* some evergreen boards have bad data for this entry */

	if (ASIC_IS_DCE4(rdev)) {

				if ((i == 7) &&

		if ((index == 7) &&

		    (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1936) &&

		    (gpio->sucI2cId.ucAccess == 0)) {

			gpio->sucI2cId.ucAccess = 0x97;
@@ -112,13 +93,19 @@ static struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_device *rd 


	/* some DCE3 boards have bad data for this entry */

	if (ASIC_IS_DCE3(rdev)) {

				if ((i == 4) &&

		if ((index == 4) &&

		    (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1fda) &&

		    (gpio->sucI2cId.ucAccess == 0x94))

			gpio->sucI2cId.ucAccess = 0x14;

	}

}



static struct radeon_i2c_bus_rec radeon_get_bus_rec_for_i2c_gpio(ATOM_GPIO_I2C_ASSIGMENT *gpio)

{

	struct radeon_i2c_bus_rec i2c;



	memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));



			if (gpio->sucI2cId.ucAccess == id) {

	i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;

	i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;

	i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
@@ -150,15 +137,14 @@ static struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_device *rd 


	if (i2c.mask_clk_reg)

		i2c.valid = true;

				break;

			}

		}

	}

	else

		i2c.valid = false;



	return i2c;

}



void radeon_atombios_i2c_init(struct radeon_device *rdev)

static struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_device *rdev,

							       uint8_t id)

{

	struct atom_context *ctx = rdev->mode_info.atom_context;

	ATOM_GPIO_I2C_ASSIGMENT *gpio;
@@ -167,9 +153,9 @@ void radeon_atombios_i2c_init(struct radeon_device *rdev) 
	struct _ATOM_GPIO_I2C_INFO *i2c_info;

	uint16_t data_offset, size;

	int i, num_indices;

	char stmp[32];



	memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));

	i2c.valid = false;



	if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {

		i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
@@ -179,72 +165,44 @@ void radeon_atombios_i2c_init(struct radeon_device *rdev) 


		for (i = 0; i < num_indices; i++) {

			gpio = &i2c_info->asGPIO_Info[i];

			i2c.valid = false;



			/* r4xx mask is technically not used by the hw, so patch in the legacy mask bits */

			if ((rdev->family == CHIP_R420) ||

			    (rdev->family == CHIP_R423) ||

			    (rdev->family == CHIP_RV410)) {

				if ((le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0018) ||

				    (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0019) ||

				    (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x001a)) {

					gpio->ucClkMaskShift = 0x19;

					gpio->ucDataMaskShift = 0x18;

				}

			}

			radeon_lookup_i2c_gpio_quirks(rdev, gpio, i);



			/* some evergreen boards have bad data for this entry */

			if (ASIC_IS_DCE4(rdev)) {

				if ((i == 7) &&

				    (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1936) &&

				    (gpio->sucI2cId.ucAccess == 0)) {

					gpio->sucI2cId.ucAccess = 0x97;

					gpio->ucDataMaskShift = 8;

					gpio->ucDataEnShift = 8;

					gpio->ucDataY_Shift = 8;

					gpio->ucDataA_Shift = 8;

			if (gpio->sucI2cId.ucAccess == id) {

				i2c = radeon_get_bus_rec_for_i2c_gpio(gpio);

				break;

			}

		}

	}



			/* some DCE3 boards have bad data for this entry */

			if (ASIC_IS_DCE3(rdev)) {

				if ((i == 4) &&

				    (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1fda) &&

				    (gpio->sucI2cId.ucAccess == 0x94))

					gpio->sucI2cId.ucAccess = 0x14;

	return i2c;

}



			i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;

			i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;

			i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;

			i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;

			i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;

			i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;

			i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;

			i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;

			i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);

			i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);

			i2c.en_clk_mask = (1 << gpio->ucClkEnShift);

			i2c.en_data_mask = (1 << gpio->ucDataEnShift);

			i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);

			i2c.y_data_mask = (1 << gpio->ucDataY_Shift);

			i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);

			i2c.a_data_mask = (1 << gpio->ucDataA_Shift);

void radeon_atombios_i2c_init(struct radeon_device *rdev)

{

	struct atom_context *ctx = rdev->mode_info.atom_context;

	ATOM_GPIO_I2C_ASSIGMENT *gpio;

	struct radeon_i2c_bus_rec i2c;

	int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);

	struct _ATOM_GPIO_I2C_INFO *i2c_info;

	uint16_t data_offset, size;

	int i, num_indices;

	char stmp[32];



			if (gpio->sucI2cId.sbfAccess.bfHW_Capable)

				i2c.hw_capable = true;

			else

				i2c.hw_capable = false;

	if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {

		i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);



			if (gpio->sucI2cId.ucAccess == 0xa0)

				i2c.mm_i2c = true;

			else

				i2c.mm_i2c = false;

		num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /

			sizeof(ATOM_GPIO_I2C_ASSIGMENT);



			i2c.i2c_id = gpio->sucI2cId.ucAccess;

		for (i = 0; i < num_indices; i++) {

			gpio = &i2c_info->asGPIO_Info[i];



			if (i2c.mask_clk_reg) {

				i2c.valid = true;

			radeon_lookup_i2c_gpio_quirks(rdev, gpio, i);



			i2c = radeon_get_bus_rec_for_i2c_gpio(gpio);



			if (i2c.valid) {

				sprintf(stmp, "0x%x", i2c.i2c_id);

				rdev->i2c_bus[i] = radeon_i2c_create(rdev->ddev, &i2c, stmp);

			}