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Commit 212154ba authored by Oscar Mateo's avatar Oscar Mateo Committed by Chris Wilson
Browse files

drm/i915: Transform WaDisablePooledEuLoadBalancingFix into a simple register write 



FF_SLICE_CS_CHICKEN2 does not belong to the context image.

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: default avatarOscar Mateo <oscar.mateo@intel.com>
Reviewed-by: default avatarMichał Winiarski <michal.winiarski@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1504798809-5653-6-git-send-email-oscar.mateo@intel.com


Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
parent c6ea497c

drivers/gpu/drm/i915/intel_engine_cs.c

+2 −2
Original line number Diff line number Diff line
@@ -1024,8 +1024,8 @@ static int bxt_init_workarounds(struct intel_engine_cs *engine) 


	/* WaDisablePooledEuLoadBalancingFix:bxt */

	if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER)) {

		WA_SET_BIT_MASKED(FF_SLICE_CS_CHICKEN2,

				  GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE);

		I915_WRITE(FF_SLICE_CS_CHICKEN2,

			   _MASKED_BIT_ENABLE(GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE));

	}



	/* WaDisableSbeCacheDispatchPortSharing:bxt */