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Commit 20c5018e authored by Jilai Wang's avatar Jilai Wang
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msm: npu: Set clock gating bit properly



Bit 1 in GPR1 was used to notify fw to enable clock gating if
set to 1. But it has been changed in fw to enable clock gating
if set to 0 recently. This change is to align with fw's change
to set this clock gating bit properly.

Change-Id: I3a83aa99d8b345f3d1f2f94ce65e55f59a689e91
Signed-off-by: default avatarJilai Wang <jilaiw@codeaurora.org>
parent 9a52f417
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