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Commit 20c5018e authored by Jilai Wang's avatar Jilai Wang
Browse files

msm: npu: Set clock gating bit properly 



Bit 1 in GPR1 was used to notify fw to enable clock gating if
set to 1. But it has been changed in fw to enable clock gating
if set to 0 recently. This change is to align with fw's change
to set this clock gating bit properly.

Change-Id: I3a83aa99d8b345f3d1f2f94ce65e55f59a689e91
Signed-off-by: default avatarJilai Wang <jilaiw@codeaurora.org>
parent 9a52f417

drivers/media/platform/msm/npu/npu_firmware.h

+5 −5
Original line number Original line Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0-only */

/* SPDX-License-Identifier: GPL-2.0-only */

/*

/*

 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.

 * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.

 */

 */





#ifndef _NPU_FIRMWARE_H

#ifndef _NPU_FIRMWARE_H
@@ -68,8 +68,8 @@ 
#define HOST_CTRL_STATUS_IPC_ADDRESS_READY_BIT      0

#define HOST_CTRL_STATUS_IPC_ADDRESS_READY_BIT      0

/* Host has enabled logging during boot */

/* Host has enabled logging during boot */

#define HOST_CTRL_STATUS_BOOT_ENABLE_LOGGING_BIT    1

#define HOST_CTRL_STATUS_BOOT_ENABLE_LOGGING_BIT    1

/* Host has enabled the clk gating of CAL during boot */

/* Host has disabled the clk gating of CAL during boot */

#define HOST_CTRL_STATUS_BOOT_ENABLE_CLK_GATE_BIT   2

#define HOST_CTRL_STATUS_BOOT_DISABLE_CLK_GATE_BIT   2

/* Host requests to pause fw during boot up */

/* Host requests to pause fw during boot up */

#define HOST_CTRL_STATUS_FW_PAUSE                   3

#define HOST_CTRL_STATUS_FW_PAUSE                   3

/* Host requests to disable watchdog */

/* Host requests to disable watchdog */
@@ -80,8 +80,8 @@ 
		(1 << HOST_CTRL_STATUS_IPC_ADDRESS_READY_BIT)

		(1 << HOST_CTRL_STATUS_IPC_ADDRESS_READY_BIT)

#define HOST_CTRL_STATUS_BOOT_ENABLE_LOGGING_VAL \

#define HOST_CTRL_STATUS_BOOT_ENABLE_LOGGING_VAL \

		(1 << HOST_CTRL_STATUS_BOOT_ENABLE_LOGGING_BIT)

		(1 << HOST_CTRL_STATUS_BOOT_ENABLE_LOGGING_BIT)

#define HOST_CTRL_STATUS_BOOT_ENABLE_CLK_GATE_VAL \

#define HOST_CTRL_STATUS_BOOT_DISABLE_CLK_GATE_VAL \

		(1 << HOST_CTRL_STATUS_BOOT_ENABLE_CLK_GATE_BIT)

		(1 << HOST_CTRL_STATUS_BOOT_DISABLE_CLK_GATE_BIT)

#define HOST_CTRL_STATUS_FW_PAUSE_VAL \

#define HOST_CTRL_STATUS_FW_PAUSE_VAL \

		(1 << HOST_CTRL_STATUS_FW_PAUSE)

		(1 << HOST_CTRL_STATUS_FW_PAUSE)

#define HOST_CTRL_STATUS_DISABLE_WDOG_VAL \

#define HOST_CTRL_STATUS_DISABLE_WDOG_VAL \

drivers/media/platform/msm/npu/npu_mgr.c

+23 −2
Original line number Original line Diff line number Diff line
@@ -313,6 +313,7 @@ static int enable_fw_nolock(struct npu_device *npu_dev) 
{

{

	struct npu_host_ctx *host_ctx = &npu_dev->host_ctx;

	struct npu_host_ctx *host_ctx = &npu_dev->host_ctx;

	int ret = 0;

	int ret = 0;

	uint32_t reg_val;





	if (host_ctx->fw_state == FW_UNLOADED) {

	if (host_ctx->fw_state == FW_UNLOADED) {

		ret = load_fw_nolock(npu_dev,

		ret = load_fw_nolock(npu_dev,
@@ -350,6 +351,26 @@ static int enable_fw_nolock(struct npu_device *npu_dev) 
		goto enable_sys_cache_fail;

		goto enable_sys_cache_fail;

	}

	}





	/* Clear control/status registers */

	REGW(npu_dev, REG_NPU_FW_CTRL_STATUS, 0x0);

	REGW(npu_dev, REG_NPU_HOST_CTRL_VALUE, 0x0);

	REGW(npu_dev, REG_FW_TO_HOST_EVENT, 0x0);



	NPU_DBG("fw_dbg_mode %x\n", host_ctx->fw_dbg_mode);

	reg_val = 0;

	if (host_ctx->fw_dbg_mode & FW_DBG_MODE_PAUSE)

		reg_val |= HOST_CTRL_STATUS_FW_PAUSE_VAL;



	if (host_ctx->fw_dbg_mode & FW_DBG_DISABLE_WDOG)

		reg_val |= HOST_CTRL_STATUS_DISABLE_WDOG_VAL;



	if (!npu_hw_clk_gating_enabled())

		reg_val |= HOST_CTRL_STATUS_BOOT_DISABLE_CLK_GATE_VAL;



	REGW(npu_dev, REG_NPU_HOST_CTRL_STATUS, reg_val);

	/* Read back to flush all registers for fw to read */

	REGR(npu_dev, REG_NPU_HOST_CTRL_STATUS);



	/* Initialize the host side IPC before fw boots up */

	/* Initialize the host side IPC before fw boots up */

	npu_host_ipc_pre_init(npu_dev);

	npu_host_ipc_pre_init(npu_dev);

	npu_host_ipc_post_init(npu_dev);

	npu_host_ipc_post_init(npu_dev);
@@ -626,8 +647,8 @@ static int npu_notifier_cb(struct notifier_block *this, unsigned long code, 
		if (host_ctx->fw_dbg_mode & FW_DBG_DISABLE_WDOG)

		if (host_ctx->fw_dbg_mode & FW_DBG_DISABLE_WDOG)

			reg_val |= HOST_CTRL_STATUS_DISABLE_WDOG_VAL;

			reg_val |= HOST_CTRL_STATUS_DISABLE_WDOG_VAL;





		if (npu_hw_clk_gating_enabled())

		if (!npu_hw_clk_gating_enabled())

			reg_val |= HOST_CTRL_STATUS_BOOT_ENABLE_CLK_GATE_VAL;

			reg_val |= HOST_CTRL_STATUS_BOOT_DISABLE_CLK_GATE_VAL;





		REGW(npu_dev, REG_NPU_HOST_CTRL_STATUS, reg_val);

		REGW(npu_dev, REG_NPU_HOST_CTRL_STATUS, reg_val);

		/* Read back to flush all registers for fw to read */

		/* Read back to flush all registers for fw to read */