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Commit 20462193 authored by Linus Torvalds's avatar Linus Torvalds
Browse files
* 'fixes-2.6.23' of git://git.kernel.org/pub/scm/linux/kernel/git/galak/powerpc:
  [POWERPC] Fix 8xx compile failure
  [POWERPC] Fix FSL BookE machine check reporting
  [POWERPC] Fix interrupt routing and setup of ULI M1575 on FSL boards
  [POWERPC] Add interrupt resource for RTC CMOS driver
parents 0c5564bd 0af666fa
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+38 −50
Original line number Diff line number Diff line
@@ -44,8 +44,18 @@
		#size-cells = <1>;
		#interrupt-cells = <2>;
		device_type = "soc";
		ranges = <0 e0000000 00100000>;
		reg = <e0000000 00100000>;	// CCSRBAR 1M


		ranges = <00001000 e0001000 000ff000
			  80000000 80000000 20000000
			  a0000000 a0000000 10000000
			  b0000000 b0000000 00100000
			  c0000000 c0000000 20000000
			  b0100000 b0100000 00100000
			  e1000000 e1000000 00010000
			  e1010000 e1010000 00010000
			  e1020000 e1020000 00010000>;
		reg = <e0000000 00001000>;	// CCSRBAR 1M
		bus-frequency = <0>;		// Filled out by uboot.

		memory-controller@2000 {
@@ -161,8 +171,8 @@
			interrupt-parent = <&mpic>;
			interrupts = <18 2>;
			bus-range = <0 ff>;
			ranges = <02000000 0 80000000 80000000 0 10000000
				  01000000 0 00000000 e2000000 0 00800000>;
			ranges = <02000000 0 c0000000 c0000000 0 20000000
				  01000000 0 00000000 e1000000 0 00010000>;
			clock-frequency = <3f940aa>;
			#interrupt-cells = <1>;
			#size-cells = <2>;
@@ -178,8 +188,8 @@
			#address-cells = <3>;
			reg = <9000 1000>;
			bus-range = <0 ff>;
			ranges = <02000000 0 90000000 90000000 0 10000000
				  01000000 0 00000000 e3000000 0 00800000>;
			ranges = <02000000 0 80000000 80000000 0 20000000
				  01000000 0 00000000 e1010000 0 00010000>;
			clock-frequency = <1fca055>;
			interrupt-parent = <&mpic>;
			interrupts = <1a 2>;
@@ -202,7 +212,7 @@
			reg = <a000 1000>;
			bus-range = <0 ff>;
			ranges = <02000000 0 a0000000 a0000000 0 10000000
				  01000000 0 00000000 e2800000 0 00800000>;
				  01000000 0 00000000 e1020000 0 00010000>;
			clock-frequency = <1fca055>;
			interrupt-parent = <&mpic>;
			interrupts = <19 2>;
@@ -224,49 +234,29 @@
			#address-cells = <3>;
			reg = <b000 1000>;
			bus-range = <0 ff>;
			ranges = <02000000 0 b0000000 b0000000 0 10000000
				  01000000 0 00000000 e3800000 0 00800000>;
			ranges = <02000000 0 b0000000 b0000000 0 00100000
				  01000000 0 00000000 b0100000 0 00100000>;
			clock-frequency = <1fca055>;
			interrupt-parent = <&mpic>;
			interrupts = <1b 2>;
			interrupt-map-mask = <f800 0 0 7>;
			interrupt-map-mask = <fb00 0 0 0>;
			interrupt-map = <

				// IDSEL 0x1a
				d000 0 0 1 &i8259 6 2
				d000 0 0 2 &i8259 3 2
				d000 0 0 3 &i8259 4 2
				d000 0 0 4 &i8259 5 2

				// IDSEL 0x1b
				d800 0 0 1 &i8259 5 2
				d800 0 0 2 &i8259 0 0
				d800 0 0 3 &i8259 0 0
				d800 0 0 4 &i8259 0 0

				// IDSEL 0x1c  USB
				e000 0 0 1 &i8259 9 2
				e000 0 0 2 &i8259 a 2
				e000 0 0 3 &i8259 c 2
				e000 0 0 4 &i8259 7 2
				e000 0 0 0 &i8259 c 2
				e100 0 0 0 &i8259 9 2
				e200 0 0 0 &i8259 a 2
				e300 0 0 0 &i8259 b 2

				// IDSEL 0x1d  Audio
				e800 0 0 1 &i8259 9 2
				e800 0 0 2 &i8259 a 2
				e800 0 0 3 &i8259 b 2
				e800 0 0 4 &i8259 0 0
				e800 0 0 0 &i8259 6 2

				// IDSEL 0x1e Legacy
				f000 0 0 1 &i8259 c 2
				f000 0 0 2 &i8259 0 0
				f000 0 0 3 &i8259 0 0
				f000 0 0 4 &i8259 0 0
				f000 0 0 0 &i8259 7 2
				f100 0 0 0 &i8259 7 2

				// IDSEL 0x1f IDE/SATA
				f800 0 0 1 &i8259 6 2
				f800 0 0 2 &i8259 0 0
				f800 0 0 3 &i8259 0 0
				f800 0 0 4 &i8259 0 0
				f800 0 0 0 &i8259 e 2
				f900 0 0 0 &i8259 5 2
			>;
			uli1575@0 {
				reg = <0 0 0 0 0>;
@@ -274,10 +264,10 @@
				#address-cells = <3>;
				ranges = <02000000 0 b0000000
					  02000000 0 b0000000
					  0 10000000
					  0 00100000
					  01000000 0 00000000
					  01000000 0 00000000
					  0 00080000>;
					  0 00100000>;

				pci_bridge@0 {
					reg = <0 0 0 0 0>;
@@ -285,7 +275,7 @@
					#address-cells = <3>;
					ranges = <02000000 0 b0000000
						  02000000 0 b0000000
						  0 20000000
						  0 00100000
						  01000000 0 00000000
						  01000000 0 00000000
						  0 00100000>; 
@@ -296,7 +286,8 @@
						#size-cells = <1>;
						#address-cells = <2>;
						reg = <f000 0 0 0 0>;
						ranges = <1 0 01000000 0 0
						ranges = <1 0
							  01000000 0 0
							  00001000>;
						interrupt-parent = <&i8259>;

@@ -312,8 +303,7 @@
							built-in;
							compatible = "chrp,iic";
							interrupts = <9 2>;
							interrupt-parent =
								<&mpic>;
							interrupt-parent = <&mpic>;
						};

						i8042@60 {
@@ -321,8 +311,7 @@
							#address-cells = <1>;
							reg = <1 60 1 1 64 1>;
							interrupts = <1 3 c 3>;
							interrupt-parent =
								<&i8259>;
							interrupt-parent = <&i8259>;

							keyboard@0 {
								reg = <0>;
@@ -336,8 +325,7 @@
						};

						rtc@70 {
							compatible =
								"pnpPNP,b00";
							compatible = "pnpPNP,b00";
							reg = <1 70 2>;
						};

+26 −88
Original line number Diff line number Diff line
@@ -224,98 +224,36 @@
			clock-frequency = <1fca055>;
			interrupt-parent = <&mpic>;
			interrupts = <18 2>;
			interrupt-map-mask = <f800 0 0 7>;
			interrupt-map-mask = <fb00 0 0 0>;
			interrupt-map = <
				/* IDSEL 0x11 */
				8800 0 0 1 &i8259 3 2
				8800 0 0 2 &i8259 4 2
				8800 0 0 3 &i8259 5 2
				8800 0 0 4 &i8259 6 2
				8800 0 0 1 &i8259 9 2
				8800 0 0 2 &i8259 a 2
				8800 0 0 3 &i8259 b 2
				8800 0 0 4 &i8259 c 2

				/* IDSEL 0x12 */
				9000 0 0 1 &i8259 4 2
				9000 0 0 2 &i8259 5 2
				9000 0 0 3 &i8259 6 2
				9000 0 0 4 &i8259 3 2

				/* IDSEL 0x13 */
				9800 0 0 1 &i8259 0 0
				9800 0 0 2 &i8259 0 0
				9800 0 0 3 &i8259 0 0
				9800 0 0 4 &i8259 0 0

				/* IDSEL 0x14 */
				a000 0 0 1 &i8259 0 0
				a000 0 0 2 &i8259 0 0
				a000 0 0 3 &i8259 0 0
				a000 0 0 4 &i8259 0 0

				/* IDSEL 0x15 */
				a800 0 0 1 &i8259 0 0
				a800 0 0 2 &i8259 0 0
				a800 0 0 3 &i8259 0 0
				a800 0 0 4 &i8259 0 0

				/* IDSEL 0x16 */
				b000 0 0 1 &i8259 0 0
				b000 0 0 2 &i8259 0 0
				b000 0 0 3 &i8259 0 0
				b000 0 0 4 &i8259 0 0

				/* IDSEL 0x17 */
				b800 0 0 1 &i8259 0 0
				b800 0 0 2 &i8259 0 0
				b800 0 0 3 &i8259 0 0
				b800 0 0 4 &i8259 0 0

				/* IDSEL 0x18 */
				c000 0 0 1 &i8259 0 0
				c000 0 0 2 &i8259 0 0
				c000 0 0 3 &i8259 0 0
				c000 0 0 4 &i8259 0 0

				/* IDSEL 0x19 */
				c800 0 0 1 &i8259 0 0
				c800 0 0 2 &i8259 0 0
				c800 0 0 3 &i8259 0 0
				c800 0 0 4 &i8259 0 0

				/* IDSEL 0x1a */
				d000 0 0 1 &i8259 6 2
				d000 0 0 2 &i8259 3 2
				d000 0 0 3 &i8259 4 2
				d000 0 0 4 &i8259 5 2


				/* IDSEL 0x1b */
				d800 0 0 1 &i8259 5 2
				d800 0 0 2 &i8259 0 0
				d800 0 0 3 &i8259 0 0
				d800 0 0 4 &i8259 0 0

				/* IDSEL 0x1c */
				e000 0 0 1 &i8259 9 2
				e000 0 0 2 &i8259 a 2
				e000 0 0 3 &i8259 c 2
				e000 0 0 4 &i8259 7 2

				/* IDSEL 0x1d */
				e800 0 0 1 &i8259 9 2
				e800 0 0 2 &i8259 a 2
				e800 0 0 3 &i8259 b 2
				e800 0 0 4 &i8259 0 0

				/* IDSEL 0x1e */
				f000 0 0 1 &i8259 c 2
				f000 0 0 2 &i8259 0 0
				f000 0 0 3 &i8259 0 0
				f000 0 0 4 &i8259 0 0

				/* IDSEL 0x1f */
				f800 0 0 1 &i8259 6 2
				f800 0 0 2 &i8259 0 0
				f800 0 0 3 &i8259 0 0
				f800 0 0 4 &i8259 0 0
				9000 0 0 1 &i8259 a 2
				9000 0 0 2 &i8259 b 2
				9000 0 0 3 &i8259 c 2
				9000 0 0 4 &i8259 9 2

				// IDSEL 0x1c  USB
				e000 0 0 0 &i8259 c 2
				e100 0 0 0 &i8259 9 2
				e200 0 0 0 &i8259 a 2
				e300 0 0 0 &i8259 b 2

				// IDSEL 0x1d  Audio
				e800 0 0 0 &i8259 6 2

				// IDSEL 0x1e Legacy
				f000 0 0 0 &i8259 7 2
				f100 0 0 0 &i8259 7 2

				// IDSEL 0x1f IDE/SATA
				f800 0 0 0 &i8259 e 2
				f900 0 0 0 &i8259 5 2
				>;
			uli1575@0 {
				reg = <0 0 0 0 0>;
+1 −3
Original line number Diff line number Diff line
@@ -299,7 +299,7 @@ static inline int check_io_access(struct pt_regs *regs)
#ifndef CONFIG_FSL_BOOKE
#define get_mc_reason(regs)	((regs)->dsisr)
#else
#define get_mc_reason(regs)	(mfspr(SPRN_MCSR))
#define get_mc_reason(regs)	(mfspr(SPRN_MCSR) & MCSR_MASK)
#endif
#define REASON_FP		ESR_FP
#define REASON_ILLEGAL		(ESR_PIL | ESR_PUO)
@@ -414,8 +414,6 @@ void machine_check_exception(struct pt_regs *regs)
		printk("Data Cache Push Parity Error\n");
	if (reason & MCSR_DCPERR)
		printk("Data Cache Parity Error\n");
	if (reason & MCSR_GL_CI)
		printk("Guarded Load or Cache-Inhibited stwcx.\n");
	if (reason & MCSR_BUS_IAERR)
		printk("Bus - Instruction Address Error\n");
	if (reason & MCSR_BUS_RAERR)
+1 −0
Original line number Diff line number Diff line
@@ -33,6 +33,7 @@ config MPC8544_DS
	bool "Freescale MPC8544 DS"
	select PPC_I8259
	select DEFAULT_UIMAGE
	select FSL_ULI1575
	help
	  This option enables support for the MPC8544 DS board

+15 −199
Original line number Diff line number Diff line
@@ -114,211 +114,25 @@ void __init mpc8544_ds_pic_init(void)
}

#ifdef CONFIG_PCI
enum pirq { PIRQA = 8, PIRQB, PIRQC, PIRQD, PIRQE, PIRQF, PIRQG, PIRQH };
extern int uses_fsl_uli_m1575;
extern int uli_exclude_device(struct pci_controller *hose,
				u_char bus, u_char devfn);

/*
 * Value in  table -- IRQ number
 */
const unsigned char uli1575_irq_route_table[16] = {
	0,		/* 0: Reserved */
	0x8,
	0,		/* 2: Reserved */
	0x2,
	0x4,
	0x5,
	0x7,
	0x6,
	0,		/* 8: Reserved */
	0x1,
	0x3,
	0x9,
	0xb,
	0,		/* 13: Reserved */
	0xd,
	0xf,
};

static int __devinit
get_pci_irq_from_of(struct pci_controller *hose, int slot, int pin)
{
	struct of_irq oirq;
	u32 laddr[3];
	struct device_node *hosenode = hose ? hose->arch_data : NULL;

	if (!hosenode)
		return -EINVAL;

	laddr[0] = (hose->first_busno << 16) | (PCI_DEVFN(slot, 0) << 8);
	laddr[1] = laddr[2] = 0;
	of_irq_map_raw(hosenode, &pin, 1, laddr, &oirq);
	DBG("mpc8544_ds: pci irq addr %x, slot %d, pin %d, irq %d\n",
	    laddr[0], slot, pin, oirq.specifier[0]);
	return oirq.specifier[0];
}

/*8259*/
static void __devinit quirk_uli1575(struct pci_dev *dev)
{
	unsigned short temp;
	struct pci_controller *hose = pci_bus_to_host(dev->bus);
	unsigned char irq2pin[16];
	unsigned long pirq_map_word = 0;
	u32 irq;
	int i;

	/*
	 * ULI1575 interrupts route setup
	 */
	memset(irq2pin, 0, 16);	/* Initialize default value 0 */

	irq2pin[6]=PIRQA+3;	/* enabled mapping for IRQ6 to PIRQD, used by SATA */

	/*
	 * PIRQE -> PIRQF mapping set manually
	 *
	 * IRQ pin   IRQ#
	 * PIRQE ---- 9
	 * PIRQF ---- 10
	 * PIRQG ---- 11
	 * PIRQH ---- 12
	 */
	for (i = 0; i < 4; i++)
		irq2pin[i + 9] = PIRQE + i;

	/* Set IRQ-PIRQ Mapping to ULI1575 */
	for (i = 0; i < 16; i++)
		if (irq2pin[i])
			pirq_map_word |= (uli1575_irq_route_table[i] & 0xf)
			    << ((irq2pin[i] - PIRQA) * 4);

	pirq_map_word |= 1<<26;	/* disable INTx in EP mode*/

	/* ULI1575 IRQ mapping conf register default value is 0xb9317542 */
	DBG("Setup ULI1575 IRQ mapping configuration register value = 0x%x\n",
		(int)pirq_map_word);
	pci_write_config_dword(dev, 0x48, pirq_map_word);

#define ULI1575_SET_DEV_IRQ(slot, pin, reg)				\
	do {								\
		int irq;						\
		irq = get_pci_irq_from_of(hose, slot, pin);		\
		if (irq > 0 && irq < 16) 				\
			pci_write_config_byte(dev, reg, irq2pin[irq]);	\
		else							\
			printk(KERN_WARNING "ULI1575 device"		\
				"(slot %d, pin %d) irq %d is invalid.\n", \
				slot, pin, irq);			\
	} while(0)

	/* USB 1.1 OHCI controller 1, slot 28, pin 1 */
	ULI1575_SET_DEV_IRQ(28, 1, 0x86);

	/* USB 1.1 OHCI controller 2, slot 28, pin 2 */
	ULI1575_SET_DEV_IRQ(28, 2, 0x87);

	/* USB 1.1 OHCI controller 3, slot 28, pin 3 */
	ULI1575_SET_DEV_IRQ(28, 3, 0x88);

	/* USB 2.0 controller, slot 28, pin 4 */
	irq = get_pci_irq_from_of(hose, 28, 4);
	if (irq >= 0 && irq <= 15)
		pci_write_config_dword(dev, 0x74, uli1575_irq_route_table[irq]);

	/* Audio controller, slot 29, pin 1 */
	ULI1575_SET_DEV_IRQ(29, 1, 0x8a);

	/* Modem controller, slot 29, pin 2 */
	ULI1575_SET_DEV_IRQ(29, 2, 0x8b);

	/* HD audio controller, slot 29, pin 3 */
	ULI1575_SET_DEV_IRQ(29, 3, 0x8c);

	/* SMB interrupt: slot 30, pin 1 */
	ULI1575_SET_DEV_IRQ(30, 1, 0x8e);

	/* PMU ACPI SCI interrupt: slot 30, pin 2 */
	ULI1575_SET_DEV_IRQ(30, 2, 0x8f);

	/* Serial ATA interrupt: slot 31, pin 1 */
	ULI1575_SET_DEV_IRQ(31, 1, 0x8d);

	/* Primary PATA IDE IRQ: 14
	 * Secondary PATA IDE IRQ: 15
	 */
	pci_write_config_byte(dev, 0x44, 0x30 | uli1575_irq_route_table[14]);
	pci_write_config_byte(dev, 0x75, uli1575_irq_route_table[15]);

	/* Set IRQ14 and IRQ15 to legacy IRQs */
	pci_read_config_word(dev, 0x46, &temp);
	temp |= 0xc000;
	pci_write_config_word(dev, 0x46, temp);

	/* Set i8259 interrupt trigger
	 * IRQ 3:  Level
	 * IRQ 4:  Level
	 * IRQ 5:  Level
	 * IRQ 6:  Level
	 * IRQ 7:  Level
	 * IRQ 9:  Level
	 * IRQ 10: Level
	 * IRQ 11: Level
	 * IRQ 12: Level
	 * IRQ 14: Edge
	 * IRQ 15: Edge
	 */
	outb(0xfa, 0x4d0);
	outb(0x1e, 0x4d1);

#undef ULI1575_SET_DEV_IRQ
}

/* SATA */
static void __devinit quirk_uli5288(struct pci_dev *dev)
static int mpc85xx_exclude_device(struct pci_controller *hose,
				   u_char bus, u_char devfn)
{
	unsigned char c;

	pci_read_config_byte(dev, 0x83, &c);
	c |= 0x80;		/* read/write lock */
	pci_write_config_byte(dev, 0x83, c);

	pci_write_config_byte(dev, 0x09, 0x01);	/* Base class code: storage */
	pci_write_config_byte(dev, 0x0a, 0x06);	/* IDE disk */

	pci_read_config_byte(dev, 0x83, &c);
	c &= 0x7f;
	pci_write_config_byte(dev, 0x83, c);
	struct device_node* node;	
	struct resource rsrc;

	pci_read_config_byte(dev, 0x84, &c);
	c |= 0x01;				/* emulated PATA mode enabled */
	pci_write_config_byte(dev, 0x84, c);
}
	node = (struct device_node *)hose->arch_data;
	of_address_to_resource(node, 0, &rsrc);

/* PATA */
static void __devinit quirk_uli5229(struct pci_dev *dev)
{
	unsigned short temp;
	pci_write_config_word(dev, 0x04, 0x0405);	/* MEM IO MSI */
	pci_read_config_word(dev, 0x4a, &temp);
	temp |= 0x1000;				/* Enable Native IRQ 14/15 */
	pci_write_config_word(dev, 0x4a, temp);
	if ((rsrc.start & 0xfffff) == 0xb000) {
		return uli_exclude_device(hose, bus, devfn);
	}

/*Bridge*/
static void __devinit early_uli5249(struct pci_dev *dev)
{
	unsigned char temp;
	pci_write_config_word(dev, 0x04, 0x0007);	/* mem access */
	pci_read_config_byte(dev, 0x7c, &temp);
	pci_write_config_byte(dev, 0x7c, 0x80);	/* R/W lock control */
	pci_write_config_byte(dev, 0x09, 0x01);	/* set as pci-pci bridge */
	pci_write_config_byte(dev, 0x7c, temp);	/* restore pci bus debug control */
	dev->class |= 0x1;
	return PCIBIOS_SUCCESSFUL;
}

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x1575, quirk_uli1575);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5288, quirk_uli5288);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5229, quirk_uli5229);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AL, 0x5249, early_uli5249);
#endif	/* CONFIG_PCI */

/*
@@ -342,6 +156,8 @@ static void __init mpc8544_ds_setup_arch(void)
		else
			fsl_add_bridge(np, 0);
	}
	uses_fsl_uli_m1575 = 1;
	ppc_md.pci_exclude_device = mpc85xx_exclude_device;
#endif

	printk("MPC8544 DS board from Freescale Semiconductor\n");
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