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Commit 1fd6d18c authored by Guru Das Srinagesh's avatar Guru Das Srinagesh
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power: smb5: add support for die/connector temp based mitigation 



Add support to configure/enable hardware controlled mitigation
based on DIE and connector temperature. H/W controlled scheme
manipulates input current limit(ICL) of charger whenever die or
connector temperature crosses configured threshold.

Change-Id: Ib7655a8709960c79c554657a5d144c0ceccb73d3
Signed-off-by: default avatarAshay Jaiswal <ashayj@codeaurora.org>
Signed-off-by: default avatarUmang Agrawal <uagrawal@codeaurora.org>
Signed-off-by: default avatarGuru Das Srinagesh <gurus@codeaurora.org>
parent 004d21ae

drivers/power/supply/qcom/qpnp-smb5.c

+131 −5
Original line number Diff line number Diff line
@@ -54,7 +54,7 @@ static struct smb_params smb5_pmi632_params = { 
	},

	.icl_stat		= {

		.name   = "input current limit status",

		.reg    = AICL_ICL_STATUS_REG,

		.reg    = ICL_STATUS_REG,

		.min_u  = 0,

		.max_u  = 3000000,

		.step_u = 50000,
@@ -251,6 +251,13 @@ static struct attribute *smb5_attrs[] = { 
};

ATTRIBUTE_GROUPS(smb5);



enum {

	BAT_THERM = 0,

	MISC_THERM,

	CONN_THERM,

	SMB_THERM,

};



#define PMI632_MAX_ICL_UA	3000000

#define PM6150_MAX_FCC_UA	3000000

static int smb5_chg_config_init(struct smb5 *chip)
@@ -324,6 +331,45 @@ static int smb5_chg_config_init(struct smb5 *chip) 
	return rc;

}



#define PULL_NO_PULL	0

#define PULL_30K	30

#define PULL_100K	100

#define PULL_400K	400

static int get_valid_pullup(int pull_up)

{

	/* pull up can only be 0/30K/100K/400K) */

	switch (pull_up) {

	case PULL_NO_PULL:

		return INTERNAL_PULL_NO_PULL;

	case PULL_30K:

		return INTERNAL_PULL_30K_PULL;

	case PULL_100K:

		return INTERNAL_PULL_100K_PULL;

	case PULL_400K:

		return INTERNAL_PULL_400K_PULL;

	default:

		return INTERNAL_PULL_100K_PULL;

	}

}



#define INTERNAL_PULL_UP_MASK	0x3

static int smb5_configure_internal_pull(struct smb_charger *chg, int type,

					int pull)

{

	int rc;

	int shift = type * 2;

	u8 mask = INTERNAL_PULL_UP_MASK << shift;

	u8 val = pull << shift;



	rc = smblib_masked_write(chg, BATIF_ADC_INTERNAL_PULL_UP_REG,

				mask, val);

	if (rc < 0)

		dev_err(chg->dev,

			"Couldn't configure ADC pull-up reg rc=%d\n", rc);



	return rc;

}



#define MICRO_1P5A			1500000

#define MICRO_P1A			100000

#define MICRO_1PA			1000000
@@ -434,6 +480,19 @@ static int smb5_parse_dt_misc(struct smb5 *chip, struct device_node *node) 
			of_property_read_bool(node,

					"qcom,uusb-moisture-protection-enable");



	chg->hw_die_temp_mitigation = of_property_read_bool(node,

					"qcom,hw-die-temp-mitigation");



	chg->hw_connector_mitigation = of_property_read_bool(node,

					"qcom,hw-connector-mitigation");



	chg->hw_skin_temp_mitigation = of_property_read_bool(node,

					"qcom,hw-skin-temp-mitigation");



	chg->connector_pull_up = -EINVAL;

	of_property_read_u32(node, "qcom,connector-internal-pull-kohm",

					&chg->connector_pull_up);



	chip->dt.disable_suspend_on_collapse = of_property_read_bool(node,

					"qcom,disable-suspend-on-collapse");
@@ -624,6 +683,7 @@ static enum power_supply_property smb5_usb_props[] = { 
	POWER_SUPPLY_PROP_SCOPE,

	POWER_SUPPLY_PROP_MOISTURE_DETECTED,

	POWER_SUPPLY_PROP_HVDCP_OPTI_ALLOWED,

	POWER_SUPPLY_PROP_QC_OPTI_DISABLE,

};



static int smb5_usb_get_prop(struct power_supply *psy,
@@ -633,6 +693,7 @@ static int smb5_usb_get_prop(struct power_supply *psy, 
	struct smb5 *chip = power_supply_get_drvdata(psy);

	struct smb_charger *chg = &chip->chg;

	int rc = 0;

	val->intval = 0;



	switch (psp) {

	case POWER_SUPPLY_PROP_PRESENT:
@@ -737,6 +798,13 @@ static int smb5_usb_get_prop(struct power_supply *psy, 
	case POWER_SUPPLY_PROP_HVDCP_OPTI_ALLOWED:

		val->intval = !chg->flash_active;

		break;

	case POWER_SUPPLY_PROP_QC_OPTI_DISABLE:

		if (chg->hw_die_temp_mitigation)

			val->intval = POWER_SUPPLY_QC_THERMAL_BALANCE_DISABLE

					| POWER_SUPPLY_QC_INOV_THERMAL_DISABLE;

		if (chg->hw_connector_mitigation)

			val->intval |= POWER_SUPPLY_QC_CTM_DISABLE;

		break;

	default:

		pr_err("get prop %d is not supported in usb\n", psp);

		rc = -EINVAL;
@@ -1907,6 +1975,54 @@ static int smb5_configure_iterm_thresholds(struct smb5 *chip) 
	return rc;

}



static int smb5_configure_mitigation(struct smb_charger *chg)

{

	int rc;

	u8 chan = 0, src_cfg = 0;



	if (!chg->hw_die_temp_mitigation && !chg->hw_connector_mitigation &&

			!chg->hw_skin_temp_mitigation) {

		src_cfg = THERMREG_SW_ICL_ADJUST_BIT;

	} else {

		if (chg->hw_die_temp_mitigation) {

			chan = DIE_TEMP_CHANNEL_EN_BIT;

			src_cfg = THERMREG_DIE_ADC_SRC_EN_BIT

				| THERMREG_DIE_CMP_SRC_EN_BIT;

		}



		if (chg->hw_connector_mitigation) {

			chan |= CONN_THM_CHANNEL_EN_BIT;

			src_cfg |= THERMREG_CONNECTOR_ADC_SRC_EN_BIT;

		}



		if (chg->hw_skin_temp_mitigation) {

			chan |= MISC_THM_CHANNEL_EN_BIT;

			src_cfg |= THERMREG_SKIN_ADC_SRC_EN_BIT;

		}



		rc = smblib_masked_write(chg, BATIF_ADC_CHANNEL_EN_REG,

			CONN_THM_CHANNEL_EN_BIT | DIE_TEMP_CHANNEL_EN_BIT |

			MISC_THM_CHANNEL_EN_BIT, chan);

		if (rc < 0) {

			dev_err(chg->dev, "Couldn't enable ADC channel rc=%d\n",

				rc);

			return rc;

		}

	}



	rc = smblib_masked_write(chg, MISC_THERMREG_SRC_CFG_REG,

		THERMREG_SW_ICL_ADJUST_BIT | THERMREG_DIE_ADC_SRC_EN_BIT |

		THERMREG_DIE_CMP_SRC_EN_BIT | THERMREG_SKIN_ADC_SRC_EN_BIT |

		SKIN_ADC_CFG_BIT | THERMREG_CONNECTOR_ADC_SRC_EN_BIT, src_cfg);

	if (rc < 0) {

		dev_err(chg->dev,

				"Couldn't configure THERM_SRC reg rc=%d\n", rc);

		return rc;

	}



	return 0;

}



static int smb5_init_dc_peripheral(struct smb_charger *chg)

{

	int rc = 0;
@@ -1980,11 +2096,10 @@ static int smb5_init_hw(struct smb5 *chip) 
			return rc;

		}

	} else {

		/* Allows software thermal regulation only */

		rc = smblib_write(chg, MISC_THERMREG_SRC_CFG_REG,

					 THERMREG_SW_ICL_ADJUST_BIT);

		/* configure temperature mitigation */

		rc = smb5_configure_mitigation(chg);

		if (rc < 0) {

			dev_err(chg->dev, "Couldn't configure SMB thermal regulation rc=%d\n",

			dev_err(chg->dev, "Couldn't configure mitigation rc=%d\n",

					rc);

			return rc;

		}
@@ -2329,6 +2444,17 @@ static int smb5_init_hw(struct smb5 *chip) 
		return rc;

	}



	if (chg->connector_pull_up != -EINVAL) {

		rc = smb5_configure_internal_pull(chg, CONN_THERM,

				get_valid_pullup(chg->connector_pull_up));

		if (rc < 0) {

			dev_err(chg->dev,

				"Couldn't configure CONN_THERM pull-up rc=%d\n",

				rc);

			return rc;

		}

	}



	return rc;

}

drivers/power/supply/qcom/smb5-lib.c

+18 −0
Original line number Diff line number Diff line
@@ -4267,6 +4267,24 @@ irqreturn_t icl_change_irq_handler(int irq, void *data) 
	struct smb_charger *chg = irq_data->parent_data;



	if (chg->mode == PARALLEL_MASTER) {

		/*

		 * Ignore if change in ICL is due to DIE temp mitigation.

		 * This is to prevent any further ICL split.

		 */

		if (chg->hw_die_temp_mitigation) {

			rc = smblib_read(chg, DIE_TEMP_STATUS_REG, &stat);

			if (rc < 0) {

				smblib_err(chg,

					"Couldn't read DIE_TEMP rc=%d\n", rc);

				return IRQ_HANDLED;

			}

			if (stat & (DIE_TEMP_UB_BIT | DIE_TEMP_LB_BIT)) {

				smblib_dbg(chg, PR_PARALLEL,

					"skip ICL change DIE_TEMP %x\n", stat);

				return IRQ_HANDLED;

			}

		}



		rc = smblib_read(chg, AICL_STATUS_REG, &stat);

		if (rc < 0) {

			smblib_err(chg, "Couldn't read AICL_STATUS rc=%d\n",

drivers/power/supply/qcom/smb5-lib.h

+4 −0
Original line number Diff line number Diff line
@@ -464,6 +464,10 @@ struct smb_charger { 
	bool			moisture_present;

	bool			uusb_moisture_protection_capable;

	bool			uusb_moisture_protection_enabled;

	bool			hw_die_temp_mitigation;

	bool			hw_connector_mitigation;

	bool			hw_skin_temp_mitigation;

	int			connector_pull_up;



	/* workaround flag */

	u32			wa_flags;

drivers/power/supply/qcom/smb5-reg.h

+19 −1
Original line number Diff line number Diff line
@@ -119,7 +119,7 @@ enum { 
 *  DCDC Peripheral Registers  *

 ********************************/

#define ICL_MAX_STATUS_REG			(DCDC_BASE + 0x06)



#define ICL_STATUS_REG				(DCDC_BASE + 0x07)

#define AICL_ICL_STATUS_REG			(DCDC_BASE + 0x08)



#define AICL_STATUS_REG				(DCDC_BASE + 0x0A)
@@ -171,6 +171,19 @@ enum { 
#define SHIP_MODE_REG				(BATIF_BASE + 0x40)

#define SHIP_MODE_EN_BIT			BIT(0)



#define BATIF_ADC_CHANNEL_EN_REG		(BATIF_BASE + 0x82)

#define CONN_THM_CHANNEL_EN_BIT			BIT(4)

#define DIE_TEMP_CHANNEL_EN_BIT			BIT(2)

#define MISC_THM_CHANNEL_EN_BIT			BIT(1)



#define BATIF_ADC_INTERNAL_PULL_UP_REG		(BATIF_BASE + 0x86)

#define INTERNAL_PULL_UP_CONN_THM_MASK		GENMASK(5, 4)

#define CONN_THM_SHIFT				4

#define INTERNAL_PULL_NO_PULL			0x00

#define INTERNAL_PULL_30K_PULL			0x01

#define INTERNAL_PULL_100K_PULL			0x02

#define INTERNAL_PULL_400K_PULL			0x03



/********************************

 *  USBIN Peripheral Registers  *

 ********************************/
@@ -481,7 +494,12 @@ enum { 


#define MISC_THERMREG_SRC_CFG_REG		(MISC_BASE + 0x70)

#define THERMREG_SW_ICL_ADJUST_BIT		BIT(7)

#define DIE_ADC_SEL_BIT				BIT(6)

#define THERMREG_SMB_ADC_SRC_EN_BIT		BIT(5)

#define THERMREG_CONNECTOR_ADC_SRC_EN_BIT	BIT(4)

#define SKIN_ADC_CFG_BIT			BIT(3)

#define THERMREG_SKIN_ADC_SRC_EN_BIT		BIT(2)

#define THERMREG_DIE_ADC_SRC_EN_BIT		BIT(1)

#define THERMREG_DIE_CMP_SRC_EN_BIT		BIT(0)



#define MISC_SMB_CFG_REG			(MISC_BASE + 0x90)