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Commit 1fc14993 authored by Linus Torvalds's avatar Linus Torvalds
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Merge tag 'char-misc-4.1-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc 

Pull char/misc driver updates from Greg KH:
 "Here's the big char/misc driver patchset for 4.1-rc1.

  Lots of different driver subsystem updates here, nothing major, full
  details are in the shortlog.

  All of this has been in linux-next for a while"

* tag 'char-misc-4.1-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc: (133 commits)
  mei: trace: remove unused TRACE_SYSTEM_STRING
  DTS: ARM: OMAP3-N900: Add lis3lv02d support
  Documentation: DT: lis302: update wakeup binding
  lis3lv02d: DT: add wakeup unit 2 and wakeup threshold
  lis3lv02d: DT: use s32 to support negative values
  Drivers: hv: hv_balloon: correctly handle num_pages>INT_MAX case
  Drivers: hv: hv_balloon: correctly handle val.freeram<num_pages case
  mei: replace check for connection instead of transitioning
  mei: use mei_cl_is_connected consistently
  mei: fix mei_poll operation
  hv_vmbus: Add gradually increased delay for retries in vmbus_post_msg()
  Drivers: hv: hv_balloon: survive ballooning request with num_pages=0
  Drivers: hv: hv_balloon: eliminate jumps in piecewiese linear floor function
  Drivers: hv: hv_balloon: do not online pages in offline blocks
  hv: remove the per-channel workqueue
  hv: don't schedule new works in vmbus_onoffer()/vmbus_onoffer_rescind()
  hv: run non-blocking message handlers in the dispatch tasklet
  coresight: moving to new "hwtracing" directory
  coresight-tmc: Adding a status interface to sysfs
  coresight: remove the unnecessary configuration coresight-default-sink
  ...
parents 41d5e08e ea5505fa

Documentation/devicetree/bindings/arm/coresight.txt

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@@ -61,7 +61,6 @@ Example: 
		compatible = "arm,coresight-etb10", "arm,primecell";

		reg = <0 0x20010000 0 0x1000>;



		coresight-default-sink;

		clocks = <&oscclk6a>;

		clock-names = "apb_pclk";

		port {

Documentation/devicetree/bindings/extcon/extcon-usb-gpio.txt

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USB GPIO Extcon device



This is a virtual device used to generate USB cable states from the USB ID pin

connected to a GPIO pin.



Required properties:

- compatible: Should be "linux,extcon-usb-gpio"

- id-gpio: gpio for USB ID pin. See gpio binding.



Example: Examples of extcon-usb-gpio node in dra7-evm.dts as listed below:

	extcon_usb1 {

		compatible = "linux,extcon-usb-gpio";

		id-gpio = <&gpio6 1 GPIO_ACTIVE_HIGH>;

	}



	&omap_dwc3_1 {

		extcon = <&extcon_usb1>;

	};

Documentation/devicetree/bindings/memory-controllers/ingenic,jz4780-nemc.txt

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* Ingenic JZ4780 NAND/external memory controller (NEMC)



This file documents the device tree bindings for the NEMC external memory

controller in Ingenic JZ4780



Required properties:

- compatible: Should be set to one of:

    "ingenic,jz4780-nemc" (JZ4780)

- reg: Should specify the NEMC controller registers location and length.

- clocks: Clock for the NEMC controller.

- #address-cells: Must be set to 2.

- #size-cells: Must be set to 1.

- ranges: A set of ranges for each bank describing the physical memory layout.

  Each should specify the following 4 integer values:



    <cs number> 0 <physical address of mapping> <size of mapping>



Each child of the NEMC node describes a device connected to the NEMC.



Required child node properties:

- reg: Should contain at least one register specifier, given in the following

  format:



    <cs number> <offset> <size>



  Multiple registers can be specified across multiple banks. This is needed,

  for example, for packaged NAND devices with multiple dies. Such devices

  should be grouped into a single node.



Optional child node properties:

- ingenic,nemc-bus-width: Specifies the bus width in bits. Defaults to 8 bits.

- ingenic,nemc-tAS: Address setup time in nanoseconds.

- ingenic,nemc-tAH: Address hold time in nanoseconds.

- ingenic,nemc-tBP: Burst pitch time in nanoseconds.

- ingenic,nemc-tAW: Access wait time in nanoseconds.

- ingenic,nemc-tSTRV: Static memory recovery time in nanoseconds.



If a child node references multiple banks in its "reg" property, the same value

for all optional parameters will be configured for all banks. If any optional

parameters are omitted, they will be left unchanged from whatever they are

configured to when the NEMC device is probed (which may be the reset value as

given in the hardware reference manual, or a value configured by the boot

loader).



Example (NEMC node with a NAND child device attached at CS1):



nemc: nemc@13410000 {

	compatible = "ingenic,jz4780-nemc";

	reg = <0x13410000 0x10000>;



	#address-cells = <2>;

	#size-cells = <1>;



	ranges = <1 0 0x1b000000 0x1000000

		  2 0 0x1a000000 0x1000000

		  3 0 0x19000000 0x1000000

		  4 0 0x18000000 0x1000000

		  5 0 0x17000000 0x1000000

		  6 0 0x16000000 0x1000000>;



	clocks = <&cgu JZ4780_CLK_NEMC>;



	nand: nand@1 {

		compatible = "ingenic,jz4780-nand";

		reg = <1 0 0x1000000>;



		ingenic,nemc-tAS = <10>;

		ingenic,nemc-tAH = <5>;

		ingenic,nemc-tBP = <10>;

		ingenic,nemc-tAW = <15>;

		ingenic,nemc-tSTRV = <100>;



		...

	};

};

Documentation/devicetree/bindings/misc/lis302.txt

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@@ -46,11 +46,18 @@ Optional properties for all bus drivers: 
				interrupt 2

 - st,wakeup-{x,y,z}-{lo,hi}:	set wakeup condition on x/y/z axis for

				upper/lower limit

 - st,wakeup-threshold:		set wakeup threshold

 - st,wakeup2-{x,y,z}-{lo,hi}:	set wakeup condition on x/y/z axis for

				upper/lower limit for second wakeup

				engine.

 - st,wakeup2-threshold:	set wakeup threshold for second wakeup

				engine.

 - st,highpass-cutoff-hz=:	1, 2, 4 or 8 for 1Hz, 2Hz, 4Hz or 8Hz of

				highpass cut-off frequency

 - st,hipass{1,2}-disable:	disable highpass 1/2.

 - st,default-rate=:		set the default rate

 - st,axis-{x,y,z}=:		set the axis to map to the three coordinates

 - st,axis-{x,y,z}=:		set the axis to map to the three coordinates.

				Negative values can be used for inverted axis.

 - st,{min,max}-limit-{x,y,z}	set the min/max limits for x/y/z axis

				(used by self-test)

Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.txt

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Qualcomm SPMI Controller (PMIC Arbiter)



The SPMI PMIC Arbiter is found on the Snapdragon 800 Series.  It is an SPMI

The SPMI PMIC Arbiter is found on Snapdragon chipsets.  It is an SPMI

controller with wrapping arbitration logic to allow for multiple on-chip

devices to control a single SPMI master.
@@ -19,6 +19,10 @@ Required properties: 
     "core" - core registers

     "intr" - interrupt controller registers

     "cnfg" - configuration registers

   Registers used only for V2 PMIC Arbiter:

     "chnls"  - tx-channel per virtual slave registers.

     "obsrvr" - rx-channel (called observer) per virtual slave registers.



- reg : address + size pairs describing the PMIC arb register sets; order must

        correspond with the order of entries in reg-names

- #address-cells : must be set to 2