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Commit 1f8bee26 authored by Rama Aparna Mallavarapu's avatar Rama Aparna Mallavarapu
Browse files

PM / devfreq: bw_hwmon: Reset clear bits for some hardware versions 



Certain versions of the hardware modules have monitor/interrupt clear
registers that are not self-clearing after being written to.
Explicitly clear those register bits after writing to them.

Change-Id: I0e6252be11d8503bcd4719480f503650e46a23ae
Signed-off-by: default avatarRohit Gupta <rohgup@codeaurora.org>
Signed-off-by: default avatarRama Aparna Mallavarapu <aparnam@codeaurora.org>
parent 6c3dd985

drivers/devfreq/bimc-bwmon.c

+17 −1
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0-only

/*

 * Copyright (c) 2014-2017, 2019, The Linux Foundation. All rights reserved.

 * Copyright (c) 2014-2018, 2019, The Linux Foundation. All rights reserved.

 */



#define pr_fmt(fmt) "bimc-bwmon: " fmt
@@ -168,6 +168,14 @@ void mon_clear(struct bwmon *m, bool clear_all, enum mon_reg_type type) 
			writel_relaxed(MON_CLEAR_ALL_BIT, MON3_CLEAR(m));

		else

			writel_relaxed(MON_CLEAR_BIT, MON3_CLEAR(m));

		/*

		 * In some hardware versions since MON3_CLEAR(m) register does

		 * not have self-clearing capability it needs to be cleared

		 * explicitly. But we also need to ensure the writes to it

		 * are successful before clearing it.

		 */

		wmb();

		writel_relaxed(0, MON3_CLEAR(m));

		break;

	}

	/*
@@ -357,6 +365,14 @@ void mon_irq_clear(struct bwmon *m, enum mon_reg_type type) 
		break;

	case MON3:

		writel_relaxed(MON3_INT_STATUS_MASK, MON3_INT_CLR(m));

		/*

		 * In some hardware versions since MON3_INT_CLEAR(m) register

		 * does not have self-clearing capability it needs to be

		 * cleared explicitly. But we also need to ensure the writes

		 * to it are successful before clearing it.

		 */

		wmb();

		writel_relaxed(0, MON3_INT_CLR(m));

		break;

	}

}