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Commit 1f7371b2 authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/amd/powerplay: add basic powerplay framework 



amdgpu_pp_ip_funcs is introduced to handle the two code paths,
the legacy one and the new powerplay implementation.

CONFIG_DRM_AMD_POWERPLAY kernel configuration option is
introduced for the powerplay component.

v4: squash in fixes
v3: register debugfs file when powerplay module enable
v2: add amdgpu_ucode_init_bo in hw init when amdgpu_powerplay enable.

Signed-off-by: default avatarRex Zhu <Rex.Zhu@amd.com>
Signed-off-by: default avatarJammy Zhou <Jammy.Zhou@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 47bf18b5

drivers/gpu/drm/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -160,6 +160,7 @@ config DRM_AMDGPU 
	  If M is selected, the module will be called amdgpu.



source "drivers/gpu/drm/amd/amdgpu/Kconfig"

source "drivers/gpu/drm/amd/powerplay/Kconfig"



source "drivers/gpu/drm/nouveau/Kconfig"

drivers/gpu/drm/amd/amdgpu/Makefile

+11 −1
Original line number Diff line number Diff line
@@ -7,7 +7,8 @@ FULL_AMD_PATH=$(src)/.. 
ccflags-y := -Iinclude/drm -I$(FULL_AMD_PATH)/include/asic_reg \

	-I$(FULL_AMD_PATH)/include \

	-I$(FULL_AMD_PATH)/amdgpu \

	-I$(FULL_AMD_PATH)/scheduler

	-I$(FULL_AMD_PATH)/scheduler \

	-I$(FULL_AMD_PATH)/powerplay/inc



amdgpu-y := amdgpu_drv.o
@@ -46,6 +47,7 @@ amdgpu-y += \ 
# add SMC block

amdgpu-y += \

	amdgpu_dpm.o \

	amdgpu_powerplay.o \

	cz_smc.o cz_dpm.o \

	tonga_smc.o tonga_dpm.o \

	fiji_smc.o fiji_dpm.o \
@@ -96,6 +98,14 @@ amdgpu-$(CONFIG_VGA_SWITCHEROO) += amdgpu_atpx_handler.o 
amdgpu-$(CONFIG_ACPI) += amdgpu_acpi.o

amdgpu-$(CONFIG_MMU_NOTIFIER) += amdgpu_mn.o



ifneq ($(CONFIG_DRM_AMD_POWERPLAY),)



include drivers/gpu/drm/amd/powerplay/Makefile



amdgpu-y += $(AMD_POWERPLAY_FILES)



endif



obj-$(CONFIG_DRM_AMDGPU)+= amdgpu.o



CFLAGS_amdgpu_trace_points.o := -I$(src)

drivers/gpu/drm/amd/amdgpu/amdgpu.h

+5 −0
Original line number Diff line number Diff line
@@ -52,6 +52,7 @@ 
#include "amdgpu_irq.h"

#include "amdgpu_ucode.h"

#include "amdgpu_gds.h"

#include "amd_powerplay.h"



#include "gpu_scheduler.h"
@@ -85,6 +86,7 @@ extern int amdgpu_enable_scheduler; 
extern int amdgpu_sched_jobs;

extern int amdgpu_sched_hw_submission;

extern int amdgpu_enable_semaphores;

extern int amdgpu_powerplay;



#define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS	        3000

#define AMDGPU_MAX_USEC_TIMEOUT			100000	/* 100 ms */
@@ -2036,6 +2038,9 @@ struct amdgpu_device { 
	/* interrupts */

	struct amdgpu_irq		irq;



	/* powerplay */

	struct amd_powerplay		powerplay;



	/* dpm */

	struct amdgpu_pm		pm;

	u32				cg_flags;

drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c

+1 −0
Original line number Diff line number Diff line
@@ -82,6 +82,7 @@ int amdgpu_enable_scheduler = 1; 
int amdgpu_sched_jobs = 32;

int amdgpu_sched_hw_submission = 2;

int amdgpu_enable_semaphores = 0;

int amdgpu_powerplay = 0;



MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");

module_param_named(vramlimit, amdgpu_vram_limit, int, 0600);

drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c

0 → 100644
+280 −0
Original line number Diff line number Diff line 
/*

 * Copyright 2015 Advanced Micro Devices, Inc.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR

 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

 * OTHER DEALINGS IN THE SOFTWARE.

 *

 * Authors: AMD

 *

 */

#include "atom.h"

#include "amdgpu.h"

#include "amd_shared.h"

#include <linux/module.h>

#include <linux/moduleparam.h>

#include "amdgpu_pm.h"

#include <drm/amdgpu_drm.h>

#include "amdgpu_powerplay.h"

#include "cik_dpm.h"

#include "vi_dpm.h"



static int amdgpu_powerplay_init(struct amdgpu_device *adev)

{

	int ret = 0;

	struct amd_powerplay *amd_pp;



	amd_pp = &(adev->powerplay);



	if (amdgpu_powerplay) {

#ifdef CONFIG_DRM_AMD_POWERPLAY

		struct amd_pp_init *pp_init;



		pp_init = kzalloc(sizeof(struct amd_pp_init), GFP_KERNEL);



		if (pp_init == NULL)

			return -ENOMEM;



		pp_init->chip_family = adev->family;

		pp_init->chip_id = adev->asic_type;

		pp_init->device = amdgpu_cgs_create_device(adev);



		ret = amd_powerplay_init(pp_init, amd_pp);

		kfree(pp_init);

#endif

	} else {

		amd_pp->pp_handle = (void *)adev;



		switch (adev->asic_type) {

#ifdef CONFIG_DRM_AMDGPU_CIK

		case CHIP_BONAIRE:

		case CHIP_HAWAII:

			amd_pp->ip_funcs = &ci_dpm_ip_funcs;

			break;

		case CHIP_KABINI:

		case CHIP_MULLINS:

		case CHIP_KAVERI:

			amd_pp->ip_funcs = &kv_dpm_ip_funcs;

			break;

#endif

		case CHIP_TOPAZ:

			amd_pp->ip_funcs = &iceland_dpm_ip_funcs;

			break;

		case CHIP_TONGA:

			amd_pp->ip_funcs = &tonga_dpm_ip_funcs;

			break;

		case CHIP_CARRIZO:

			amd_pp->ip_funcs = &cz_dpm_ip_funcs;

			break;

		default:

			ret = -EINVAL;

			break;

		}

	}

	return ret;

}



static int amdgpu_pp_early_init(void *handle)

{

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	int ret = 0;



	ret = amdgpu_powerplay_init(adev);

	if (ret)

		return ret;



	if (adev->powerplay.ip_funcs->early_init)

		ret = adev->powerplay.ip_funcs->early_init(

					adev->powerplay.pp_handle);

	return ret;

}



static int amdgpu_pp_sw_init(void *handle)

{

	int ret = 0;

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;



	if (adev->powerplay.ip_funcs->sw_init)

		ret = adev->powerplay.ip_funcs->sw_init(

					adev->powerplay.pp_handle);



#ifdef CONFIG_DRM_AMD_POWERPLAY

	if (amdgpu_powerplay) {

		adev->pm.dpm_enabled = true;

		amdgpu_pm_sysfs_init(adev);

	}

#endif



	return ret;

}



static int amdgpu_pp_sw_fini(void *handle)

{

	int ret = 0;

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;



	if (adev->powerplay.ip_funcs->sw_fini)

		ret = adev->powerplay.ip_funcs->sw_fini(

					adev->powerplay.pp_handle);

	if (ret)

		return ret;



#ifdef CONFIG_DRM_AMD_POWERPLAY

	if (amdgpu_powerplay) {

		amdgpu_pm_sysfs_fini(adev);

		amd_powerplay_fini(adev->powerplay.pp_handle);

	}

#endif



	return ret;

}



static int amdgpu_pp_hw_init(void *handle)

{

	int ret = 0;

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;



	if (amdgpu_powerplay && adev->firmware.smu_load)

		amdgpu_ucode_init_bo(adev);



	if (adev->powerplay.ip_funcs->hw_init)

		ret = adev->powerplay.ip_funcs->hw_init(

					adev->powerplay.pp_handle);



	return ret;

}



static int amdgpu_pp_hw_fini(void *handle)

{

	int ret = 0;

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;



	if (adev->powerplay.ip_funcs->hw_fini)

		ret = adev->powerplay.ip_funcs->hw_fini(

					adev->powerplay.pp_handle);



	if (amdgpu_powerplay && adev->firmware.smu_load)

		amdgpu_ucode_fini_bo(adev);



	return ret;

}



static int amdgpu_pp_suspend(void *handle)

{

	int ret = 0;

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;



	if (adev->powerplay.ip_funcs->suspend)

		ret = adev->powerplay.ip_funcs->suspend(

					 adev->powerplay.pp_handle);

	return ret;

}



static int amdgpu_pp_resume(void *handle)

{

	int ret = 0;

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;



	if (adev->powerplay.ip_funcs->resume)

		ret = adev->powerplay.ip_funcs->resume(

					adev->powerplay.pp_handle);

	return ret;

}



static int amdgpu_pp_set_clockgating_state(void *handle,

					enum amd_clockgating_state state)

{

	int ret = 0;

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;



	if (adev->powerplay.ip_funcs->set_clockgating_state)

		ret = adev->powerplay.ip_funcs->set_clockgating_state(

				adev->powerplay.pp_handle, state);

	return ret;

}



static int amdgpu_pp_set_powergating_state(void *handle,

					enum amd_powergating_state state)

{

	int ret = 0;

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;



	if (adev->powerplay.ip_funcs->set_powergating_state)

		ret = adev->powerplay.ip_funcs->set_powergating_state(

				 adev->powerplay.pp_handle, state);

	return ret;

}





static bool amdgpu_pp_is_idle(void *handle)

{

	bool ret = true;

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;



	if (adev->powerplay.ip_funcs->is_idle)

		ret = adev->powerplay.ip_funcs->is_idle(

					adev->powerplay.pp_handle);

	return ret;

}



static int amdgpu_pp_wait_for_idle(void *handle)

{

	int ret = 0;

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;



	if (adev->powerplay.ip_funcs->wait_for_idle)

		ret = adev->powerplay.ip_funcs->wait_for_idle(

					adev->powerplay.pp_handle);

	return ret;

}



static int amdgpu_pp_soft_reset(void *handle)

{

	int ret = 0;

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;



	if (adev->powerplay.ip_funcs->soft_reset)

		ret = adev->powerplay.ip_funcs->soft_reset(

					adev->powerplay.pp_handle);

	return ret;

}



static void amdgpu_pp_print_status(void *handle)

{

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;



	if (adev->powerplay.ip_funcs->print_status)

		adev->powerplay.ip_funcs->print_status(

					adev->powerplay.pp_handle);

}



const struct amd_ip_funcs amdgpu_pp_ip_funcs = {

	.early_init = amdgpu_pp_early_init,

	.late_init = NULL,

	.sw_init = amdgpu_pp_sw_init,

	.sw_fini = amdgpu_pp_sw_fini,

	.hw_init = amdgpu_pp_hw_init,

	.hw_fini = amdgpu_pp_hw_fini,

	.suspend = amdgpu_pp_suspend,

	.resume = amdgpu_pp_resume,

	.is_idle = amdgpu_pp_is_idle,

	.wait_for_idle = amdgpu_pp_wait_for_idle,

	.soft_reset = amdgpu_pp_soft_reset,

	.print_status = amdgpu_pp_print_status,

	.set_clockgating_state = amdgpu_pp_set_clockgating_state,

	.set_powergating_state = amdgpu_pp_set_powergating_state,

};