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Commit 1f5531c9 authored by Venkat Chinta's avatar Venkat Chinta
Browse files

msm: camera: vfe: Multiple fixes 



This change sets the VFE reset IRQ mask based on hw version
and programs a default value to core cfg. This default
value is needed until support for programming is added.

Change-Id: I29a8ded9c365decbc8a2849faf05b124e8d120fc
Signed-off-by: default avatarVenkat Chinta <vchinta@codeaurora.org>
parent 02a7b1e4

drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/cam_vfe_core.c

+14 −5
Original line number Diff line number Diff line
@@ -49,11 +49,6 @@ static uint32_t rdi_irq_reg_mask[CAM_IFE_IRQ_REGISTERS_MAX] = { 
	0x00000000,

};



static uint32_t top_reset_irq_reg_mask[CAM_IFE_IRQ_REGISTERS_MAX] = {

	0x80000000,

	0x00000000,

};



static int cam_vfe_get_evt_payload(struct cam_vfe_hw_core_info *core_info,

	struct cam_vfe_top_irq_evt_payload    **evt_payload)

{
@@ -399,6 +394,7 @@ int cam_vfe_reset(void *hw_priv, void *reset_core_args, uint32_t arg_size) 
	struct cam_hw_info *vfe_hw  = hw_priv;

	struct cam_hw_soc_info *soc_info = NULL;

	struct cam_vfe_hw_core_info *core_info = NULL;

	uint32_t top_reset_irq_reg_mask[CAM_IFE_IRQ_REGISTERS_MAX];

	int rc;



	CAM_DBG(CAM_ISP, "Enter");
@@ -418,6 +414,19 @@ int cam_vfe_reset(void *hw_priv, void *reset_core_args, uint32_t arg_size) 
	core_info->irq_payload.core_info = core_info;

	core_info->irq_payload.reset_complete = &vfe_hw->hw_complete;



	memset(top_reset_irq_reg_mask, 0, sizeof(top_reset_irq_reg_mask));



	switch (vfe_hw->soc_info.hw_version) {

	case CAM_CPAS_TITAN_480_V100:

		top_reset_irq_reg_mask[CAM_IFE_IRQ_CAMIF_REG_STATUS0]

			= 0x00000001;

		break;

	default:

		top_reset_irq_reg_mask[CAM_IFE_IRQ_CAMIF_REG_STATUS0]

			= 0x80000000;

		break;

	}



	core_info->irq_handle = cam_irq_controller_subscribe_irq(

		core_info->vfe_irq_controller, CAM_IRQ_PRIORITY_0,

		top_reset_irq_reg_mask, &core_info->irq_payload,

drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe17x/cam_vfe480.h

+1 −0
Original line number Diff line number Diff line
@@ -64,6 +64,7 @@ static struct cam_vfe_camif_ver3_reg_data vfe_480_camif_reg_data = { 
	.lcr_extern_reg_update_shift     = 16,

	.dual_pd_extern_reg_update_shift = 17,

	.extern_reg_update_mask          = 1,

	.dual_ife_pix_en_shift           = 3,

	.pixel_pattern_shift             = 24,

	.pixel_pattern_mask              = 0x7,

	.dsp_mode_shift                  = 24,

drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_camif_ver3.c

+9 −2
Original line number Diff line number Diff line
@@ -18,7 +18,7 @@ 
#include "cam_cpas_api.h"



#define CAM_VFE_CAMIF_IRQ_SOF_DEBUG_CNT_MAX 2

#define CAM_VFE_CAMIF_VER3_CORE_CFG_0_DEFAULT 0x2800

#define CAM_VFE_CAMIF_VER3_CORE_CFG_0_DEFAULT 0x78002800



struct cam_vfe_mux_camif_ver3_data {

	void __iomem                                *mem_base;
@@ -259,8 +259,11 @@ static int cam_vfe_camif_ver3_resource_start( 
	CAM_DBG(CAM_ISP, "write module_cfg val = 0x%x", val);



	val = cam_io_r_mb(rsrc_data->mem_base +

		rsrc_data->camif_reg->module_cfg);

		rsrc_data->common_reg->core_cfg_0);



	/* Programming to default value must be removed once uapis have been

	 * updated to receive this programming from userspace.

	 */

	val |= CAM_VFE_CAMIF_VER3_CORE_CFG_0_DEFAULT;



	/* AF stitching by hw disabled by default
@@ -279,6 +282,10 @@ static int cam_vfe_camif_ver3_resource_start( 
	if (rsrc_data->sync_mode == CAM_ISP_HW_SYNC_SLAVE)

		val |= (1 << rsrc_data->reg_data->pp_extern_reg_update_shift);



	if ((rsrc_data->sync_mode == CAM_ISP_HW_SYNC_SLAVE) ||

		(rsrc_data->sync_mode == CAM_ISP_HW_SYNC_MASTER))

		val |= (1 << rsrc_data->reg_data->dual_ife_pix_en_shift);



	cam_io_w_mb(val, rsrc_data->mem_base +

		rsrc_data->common_reg->core_cfg_0);

drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_camif_ver3.h

+1 −0
Original line number Diff line number Diff line
@@ -37,6 +37,7 @@ struct cam_vfe_camif_ver3_reg_data { 
	uint32_t     lcr_extern_reg_update_shift;

	uint32_t     dual_pd_extern_reg_update_shift;

	uint32_t     extern_reg_update_mask;

	uint32_t     dual_ife_pix_en_shift;



	uint32_t     pixel_pattern_shift;

	uint32_t     pixel_pattern_mask;

drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_top_ver3.c

+3 −12
Original line number Diff line number Diff line
@@ -13,8 +13,7 @@ 
#include "cam_cpas_api.h"

#include "cam_vfe_soc.h"



#define CAM_VFE_HW_RESET_HW_AND_REG_VAL       0x00003F9F

#define CAM_VFE_HW_RESET_HW_VAL               0x00003F87

#define CAM_VFE_VER3_HW_RESET_HW_AND_REG_VAL  0xFFFF03FF

#define CAM_VFE_DELAY_BW_REDUCTION_NUM_FRAMES 3



struct cam_vfe_top_ver3_common_data {
@@ -428,22 +427,14 @@ int cam_vfe_top_ver3_reset(void *device_priv, 
	struct cam_vfe_top_ver3_priv   *top_priv = device_priv;

	struct cam_hw_soc_info         *soc_info = NULL;

	struct cam_vfe_top_ver3_reg_offset_common *reg_common = NULL;

	uint32_t *reset_reg_args = reset_core_args;

	uint32_t reset_reg_val;



	if (!top_priv || !reset_reg_args) {

	if (!top_priv) {

		CAM_ERR(CAM_ISP, "Invalid arguments");

		return -EINVAL;

	}



	switch (*reset_reg_args) {

	case CAM_VFE_HW_RESET_HW_AND_REG:

		reset_reg_val = CAM_VFE_HW_RESET_HW_AND_REG_VAL;

		break;

	default:

		reset_reg_val = CAM_VFE_HW_RESET_HW_VAL;

		break;

	}

	reset_reg_val = CAM_VFE_VER3_HW_RESET_HW_AND_REG_VAL;



	CAM_DBG(CAM_ISP, "reset reg value: %x", reset_reg_val);

	soc_info = top_priv->common_data.soc_info;