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Commit 1f177a13 authored by Chris Wilson's avatar Chris Wilson
Browse files

drm/i915: Use memset64() to align the ring with MI_NOOP 



When filling the ring to align the emit pointer to the next cacheline,
use memset64() rather than open-coding it. As we know that we always
have an even number of dwords, we can replace the dword loop with the
qword equivalent.

v2: s/0/MI_NOOP<<32 | MI_NOOP/

Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: default avatarTvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180425123718.16366-1-chris@chris-wilson.co.uk
parent 14d4e522

drivers/gpu/drm/i915/intel_ringbuffer.c

+8 −6
Original line number Original line Diff line number Diff line
@@ -1717,22 +1717,24 @@ u32 *intel_ring_begin(struct i915_request *rq, unsigned int num_dwords) 
/* Align the ring tail to a cacheline boundary */

/* Align the ring tail to a cacheline boundary */

int intel_ring_cacheline_align(struct i915_request *rq)

int intel_ring_cacheline_align(struct i915_request *rq)

{

{

	int num_dwords = (rq->ring->emit & (CACHELINE_BYTES - 1)) / sizeof(u32);

	int num_dwords;

	u32 *cs;

	void *cs;





	num_dwords = (rq->ring->emit & (CACHELINE_BYTES - 1)) / sizeof(u32);

	if (num_dwords == 0)

	if (num_dwords == 0)

		return 0;

		return 0;





	num_dwords = CACHELINE_BYTES / sizeof(u32) - num_dwords;

	num_dwords = CACHELINE_DWORDS - num_dwords;

	GEM_BUG_ON(num_dwords & 1);



	cs = intel_ring_begin(rq, num_dwords);

	cs = intel_ring_begin(rq, num_dwords);

	if (IS_ERR(cs))

	if (IS_ERR(cs))

		return PTR_ERR(cs);

		return PTR_ERR(cs);





	while (num_dwords--)

	memset64(cs, (u64)MI_NOOP << 32 | MI_NOOP, num_dwords / 2);

		*cs++ = MI_NOOP;



	intel_ring_advance(rq, cs);

	intel_ring_advance(rq, cs);





	GEM_BUG_ON(rq->ring->emit & (CACHELINE_BYTES - 1));

	return 0;

	return 0;

}

}