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Commit 1eaff710 authored by Jon Hunter's avatar Jon Hunter
Browse files

ARM: OMAP: Don't restore DMTIMER interrupt status register 



Restoring the timer interrupt status is not possible because writing a 1 to any
bit in the register clears that bit if set and writing a 0 has no affect.
Furthermore, if an interrupt is pending when someone attempts to disable a
timer, the timer will fail to transition to the idle state and hence it's
context will not be lost. Users should take care to service all interrupts
before disabling the timer.

Signed-off-by: default avatarJon Hunter <jon-hunter@ti.com>
Acked-by: default avatarSantosh Shilimkar <santosh.shilimkar@ti.com>
parent d3004bb4

arch/arm/plat-omap/dmtimer.c

+1 −4
Original line number Diff line number Diff line
@@ -83,7 +83,6 @@ static void omap_dm_timer_write_reg(struct omap_dm_timer *timer, u32 reg, 


static void omap_timer_restore_context(struct omap_dm_timer *timer)

{

	__raw_writel(timer->context.tisr, timer->irq_stat);

	omap_dm_timer_write_reg(timer, OMAP_TIMER_WAKEUP_EN_REG,

				timer->context.twer);

	omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG,
@@ -440,7 +439,6 @@ int omap_dm_timer_stop(struct omap_dm_timer *timer) 
	 */

	timer->context.tclr =

			omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);

	timer->context.tisr = __raw_readl(timer->irq_stat);

	omap_dm_timer_disable(timer);

	return 0;

}
@@ -684,8 +682,7 @@ int omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value) 
		return -EINVAL;



	__omap_dm_timer_write_status(timer, value);

	/* Save the context */

	timer->context.tisr = value;



	return 0;

}

EXPORT_SYMBOL_GPL(omap_dm_timer_write_status);

arch/arm/plat-omap/include/plat/dmtimer.h

+0 −1
Original line number Diff line number Diff line
@@ -84,7 +84,6 @@ struct omap_dm_timer; 


struct timer_regs {

	u32 tidr;

	u32 tisr;

	u32 tier;

	u32 twer;

	u32 tclr;