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Commit 1e998343 authored by Jeff McGee's avatar Jeff McGee Committed by Chris Wilson
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drm/i915/preempt: Fix WaEnablePreemptionGranularityControlByUMD 



The WA applies to all production Gen9 and requires both enabling and
whitelisting of the per-context preemption control register.

v2: Extend to Cannonlake.

Signed-off-by: default avatarJeff McGee <jeff.mcgee@intel.com>
Signed-off-by: default avatarMichał Winiarski <michal.winiarski@intel.com>
Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: default avatarJoonas Lahtinen <joonas.lahtinen@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20171003203453.15692-1-chris@chris-wilson.co.uk
parent 3af7a9c6

drivers/gpu/drm/i915/intel_engine_cs.c

+6 −10
Original line number Diff line number Diff line
@@ -1075,7 +1075,9 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine) 
	if (ret)

		return ret;



	/* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl,cfl */

	/* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl,cfl,[cnl] */

	I915_WRITE(GEN7_FF_SLICE_CS_CHICKEN1,

		   _MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL));

	ret = wa_ring_whitelist_reg(engine, GEN8_CS_CHICKEN1);

	if (ret)

		return ret;
@@ -1138,14 +1140,6 @@ static int skl_init_workarounds(struct intel_engine_cs *engine) 
	if (ret)

		return ret;



	/*

	 * Actual WA is to disable percontext preemption granularity control

	 * until D0 which is the default case so this is equivalent to

	 * !WaDisablePerCtxtPreemptionGranularityControl:skl

	 */

	I915_WRITE(GEN7_FF_SLICE_CS_CHICKEN1,

		   _MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL));



	/* WaEnableGapsTsvCreditFix:skl */

	I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |

				   GEN9_GAPS_TSV_CREDIT_DISABLE));
@@ -1278,6 +1272,8 @@ static int cnl_init_workarounds(struct intel_engine_cs *engine) 
	WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, CNL_FAST_ANISO_L1_BANKING_FIX);



	/* WaEnablePreemptionGranularityControlByUMD:cnl */

	I915_WRITE(GEN7_FF_SLICE_CS_CHICKEN1,

		   _MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL));

	ret= wa_ring_whitelist_reg(engine, GEN8_CS_CHICKEN1);

	if (ret)

		return ret;