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Commit 1e4652c2 authored by qctecmdr Service's avatar qctecmdr Service Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: add third cluster support for Kona"

parents d3658745 86db38d3

arch/arm64/boot/dts/qcom/kona.dtsi

+11 −1
Original line number Diff line number Diff line
@@ -46,6 +46,7 @@ 
			cpu-release-addr = <0x0 0x90000000>;

			next-level-cache = <&L2_0>;

			qcom,freq-domain = <&cpufreq_hw 0 4>;

			capacity-dmips-mhz = <1024>;

			L2_0: l2-cache {

			      compatible = "arm,arch-cache";

			      cache-size = <0x20000>;
@@ -69,6 +70,7 @@ 
			cpu-release-addr = <0x0 0x90000000>;

			next-level-cache = <&L2_1>;

			qcom,freq-domain = <&cpufreq_hw 0 4>;

			capacity-dmips-mhz = <1024>;

			L2_1: l2-cache {

			      compatible = "arm,arch-cache";

			      cache-size = <0x20000>;
@@ -86,6 +88,7 @@ 
			cpu-release-addr = <0x0 0x90000000>;

			next-level-cache = <&L2_2>;

			qcom,freq-domain = <&cpufreq_hw 0 4>;

			capacity-dmips-mhz = <1024>;

			L2_2: l2-cache {

			      compatible = "arm,arch-cache";

			      cache-size = <0x20000>;
@@ -103,6 +106,7 @@ 
			cpu-release-addr = <0x0 0x90000000>;

			next-level-cache = <&L2_3>;

			qcom,freq-domain = <&cpufreq_hw 0 4>;

			capacity-dmips-mhz = <1024>;

			L2_3: l2-cache {

			      compatible = "arm,arch-cache";

			      cache-size = <0x20000>;
@@ -120,6 +124,7 @@ 
			cpu-release-addr = <0x0 0x90000000>;

			next-level-cache = <&L2_4>;

			qcom,freq-domain = <&cpufreq_hw 1 4>;

			capacity-dmips-mhz = <1894>;

			L2_4: l2-cache {

			      compatible = "arm,arch-cache";

			      cache-size = <0x20000>;
@@ -137,6 +142,7 @@ 
			cpu-release-addr = <0x0 0x90000000>;

			next-level-cache = <&L2_5>;

			qcom,freq-domain = <&cpufreq_hw 1 4>;

			capacity-dmips-mhz = <1894>;

			L2_5: l2-cache {

			      compatible = "arm,arch-cache";

			      cache-size = <0x20000>;
@@ -154,6 +160,7 @@ 
			cpu-release-addr = <0x0 0x90000000>;

			next-level-cache = <&L2_6>;

			qcom,freq-domain = <&cpufreq_hw 1 4>;

			capacity-dmips-mhz = <1894>;

			L2_6: l2-cache {

			      compatible = "arm,arch-cache";

			      cache-size = <0x20000>;
@@ -171,6 +178,7 @@ 
			cpu-release-addr = <0x0 0x90000000>;

			next-level-cache = <&L2_7>;

			qcom,freq-domain = <&cpufreq_hw 2 4>;

			capacity-dmips-mhz = <1894>;

			L2_7: l2-cache {

			      compatible = "arm,arch-cache";

			      cache-size = <0x80000>;
@@ -210,8 +218,10 @@ 
				core2 {

					cpu = <&CPU6>;

				};

			};



				core3 {

			cluster2 {

				core0 {

					cpu = <&CPU7>;

				};

			};