drm/nouveau/fb/gddr5: modify mr8 with high bits of CL/WR (1e1d6b4c) · Commits · e / devices / android_kernel_fairphone_FP4

drivers/gpu/drm/nouveau/core/subdev/fb/gddr5.c

+4 −0

Original line number	Diff line number	Diff line
		@@ -105,5 +105,9 @@ nouveau_gddr5_calc(struct nouveau_ram *ram, bool nuts)
		ram->mr[7] \|= (vr & 0x01) << 8;
		ram->mr[7] \|= (vh & 0x01) << 7;
		ram->mr[7] \|= (lf & 0x01) << 3;

		ram->mr[8] &= ~0x003;
		ram->mr[8] \|= (WR & 0x10) >> 3;
		ram->mr[8] \|= (CL & 0x10) >> 4;
		return 0;
		}