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Commit 1e09b053 authored by Hawking Zhang's avatar Hawking Zhang Committed by Alex Deucher
Browse files

drm/amdgpu: query vram type from atombios 



The vram type for dGPU is stored in umc_info while sys mem type
for APU is stored in integratedsysteminfo

Signed-off-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent bc227cfa

drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c

+91 −4
Original line number Diff line number Diff line
@@ -114,6 +114,9 @@ union igp_info { 
	struct atom_integrated_system_info_v1_11 v11;

};



union umc_info {

	struct atom_umc_info_v3_1 v31;

};

/*

 * Return vram width from integrated system info table, if available,

 * or 0 if not.
@@ -143,6 +146,94 @@ int amdgpu_atomfirmware_get_vram_width(struct amdgpu_device *adev) 
	return 0;

}



static int convert_atom_mem_type_to_vram_type (struct amdgpu_device *adev,

					       int atom_mem_type)

{

	int vram_type;



	if (adev->flags & AMD_IS_APU) {

		switch (atom_mem_type) {

		case Ddr2MemType:

		case LpDdr2MemType:

			vram_type = AMDGPU_VRAM_TYPE_DDR2;

			break;

		case Ddr3MemType:

		case LpDdr3MemType:

			vram_type = AMDGPU_VRAM_TYPE_DDR3;

			break;

		case Ddr4MemType:

		case LpDdr4MemType:

			vram_type = AMDGPU_VRAM_TYPE_DDR4;

			break;

		default:

			vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;

			break;

		}

	} else {

		switch (atom_mem_type) {

		case ATOM_DGPU_VRAM_TYPE_GDDR5:

			vram_type = AMDGPU_VRAM_TYPE_GDDR5;

			break;

		case ATOM_DGPU_VRAM_TYPE_HBM:

			vram_type = AMDGPU_VRAM_TYPE_HBM;

			break;

		default:

			vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;

			break;

		}

	}



	return vram_type;

}

/*

 * Return vram type from either integrated system info table

 * or umc info table, if available, or 0 (TYPE_UNKNOWN) if not

 */

int amdgpu_atomfirmware_get_vram_type(struct amdgpu_device *adev)

{

	struct amdgpu_mode_info *mode_info = &adev->mode_info;

	int index;

	u16 data_offset, size;

	union igp_info *igp_info;

	union umc_info *umc_info;

	u8 frev, crev;

	u8 mem_type;



	if (adev->flags & AMD_IS_APU)

		index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,

						    integratedsysteminfo);

	else

		index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,

						    umc_info);

	if (amdgpu_atom_parse_data_header(mode_info->atom_context,

					  index, &size,

					  &frev, &crev, &data_offset)) {

		if (adev->flags & AMD_IS_APU) {

			igp_info = (union igp_info *)

				(mode_info->atom_context->bios + data_offset);

			switch (crev) {

			case 11:

				mem_type = igp_info->v11.memorytype;

				return convert_atom_mem_type_to_vram_type(adev, mem_type);

			default:

				return 0;

			}

		} else {

			umc_info = (union umc_info *)

				(mode_info->atom_context->bios + data_offset);

			switch (crev) {

			case 1:

				mem_type = umc_info->v31.vram_type;

				return convert_atom_mem_type_to_vram_type(adev, mem_type);

			default:

				return 0;

			}

		}

	}



	return 0;

}



union firmware_info {

	struct atom_firmware_info_v3_1 v31;

};
@@ -151,10 +242,6 @@ union smu_info { 
	struct atom_smu_info_v3_1 v31;

};



union umc_info {

	struct atom_umc_info_v3_1 v31;

};



int amdgpu_atomfirmware_get_clock_info(struct amdgpu_device *adev)

{

	struct amdgpu_mode_info *mode_info = &adev->mode_info;

drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h

+1 −0
Original line number Diff line number Diff line
@@ -28,6 +28,7 @@ bool amdgpu_atomfirmware_gpu_supports_virtualization(struct amdgpu_device *adev) 
void amdgpu_atomfirmware_scratch_regs_init(struct amdgpu_device *adev);

int amdgpu_atomfirmware_allocate_fb_scratch(struct amdgpu_device *adev);

int amdgpu_atomfirmware_get_vram_width(struct amdgpu_device *adev);

int amdgpu_atomfirmware_get_vram_type(struct amdgpu_device *adev);

int amdgpu_atomfirmware_get_clock_info(struct amdgpu_device *adev);



#endif

drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c

+1 −3
Original line number Diff line number Diff line
@@ -836,9 +836,9 @@ static int gmc_v9_0_sw_init(void *handle) 


	spin_lock_init(&adev->gmc.invalidate_lock);



	adev->gmc.vram_type = amdgpu_atomfirmware_get_vram_type(adev);

	switch (adev->asic_type) {

	case CHIP_RAVEN:

		adev->gmc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;

		if (adev->rev_id == 0x0 || adev->rev_id == 0x1) {

			amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);

		} else {
@@ -849,8 +849,6 @@ static int gmc_v9_0_sw_init(void *handle) 
		}

		break;

	case CHIP_VEGA10:

		/* XXX Don't know how to get VRAM type yet. */

		adev->gmc.vram_type = AMDGPU_VRAM_TYPE_HBM;

		/*

		 * To fulfill 4-level page support,

		 * vm size is 256TB (48bit), maximum size of Vega10,

include/uapi/drm/amdgpu_drm.h

+1 −0
Original line number Diff line number Diff line
@@ -806,6 +806,7 @@ struct drm_amdgpu_info_firmware { 
#define AMDGPU_VRAM_TYPE_GDDR5 5

#define AMDGPU_VRAM_TYPE_HBM   6

#define AMDGPU_VRAM_TYPE_DDR3  7

#define AMDGPU_VRAM_TYPE_DDR4  8



struct drm_amdgpu_info_device {

	/** PCI Device ID */