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Commit 1dd1ea8e authored by Nicolas Ferre's avatar Nicolas Ferre Committed by Vinod Koul
Browse files

dmaengine: at_hdmac: take maxburst from slave configuration 



The maxburst/chunk size was taken from the private slave DMA data structure.
Use the common API provided by DMA_SLAVE_CONFIG to setup src/dst maxburst
values.
The ctrla field is not needed anymore in the slave private structure nor the
header constants that were located in an architecture specific directory.
The at91sam9g45_devices.c file that was using this platform data is also
modified to remove this now useless data.

Signed-off-by: default avatarNicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: default avatarVinod Koul <vinod.koul@linux.intel.com>
parent b409ebfb

arch/arm/mach-at91/at91sam9g45_devices.c

+0 −1
Original line number Diff line number Diff line
@@ -439,7 +439,6 @@ void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data) 
	atslave->dma_dev = &at_hdmac_device.dev;

	atslave->cfg = ATC_FIFOCFG_HALFFIFO

			| ATC_SRC_H2SEL_HW | ATC_DST_H2SEL_HW;

	atslave->ctrla = ATC_SCSIZE_16 | ATC_DCSIZE_16;

	if (mmc_id == 0)	/* MCI0 */

		atslave->cfg |= ATC_SRC_PER(AT_DMA_ID_MCI0)

			      | ATC_DST_PER(AT_DMA_ID_MCI0);

arch/arm/mach-at91/include/mach/at_hdmac.h

+0 −21
Original line number Diff line number Diff line
@@ -27,12 +27,10 @@ struct at_dma_platform_data { 
 * struct at_dma_slave - Controller-specific information about a slave

 * @dma_dev: required DMA master device

 * @cfg: Platform-specific initializer for the CFG register

 * @ctrla: Platform-specific initializer for the CTRLA register

 */

struct at_dma_slave {

	struct device		*dma_dev;

	u32			cfg;

	u32			ctrla;

};
@@ -59,24 +57,5 @@ struct at_dma_slave { 
#define		ATC_FIFOCFG_HALFFIFO		(0x1 << 28)

#define		ATC_FIFOCFG_ENOUGHSPACE		(0x2 << 28)



/* Platform-configurable bits in CTRLA */

#define	ATC_SCSIZE_MASK		(0x7 << 16)	/* Source Chunk Transfer Size */

#define		ATC_SCSIZE_1		(0x0 << 16)

#define		ATC_SCSIZE_4		(0x1 << 16)

#define		ATC_SCSIZE_8		(0x2 << 16)

#define		ATC_SCSIZE_16		(0x3 << 16)

#define		ATC_SCSIZE_32		(0x4 << 16)

#define		ATC_SCSIZE_64		(0x5 << 16)

#define		ATC_SCSIZE_128		(0x6 << 16)

#define		ATC_SCSIZE_256		(0x7 << 16)

#define	ATC_DCSIZE_MASK		(0x7 << 20)	/* Destination Chunk Transfer Size */

#define		ATC_DCSIZE_1		(0x0 << 20)

#define		ATC_DCSIZE_4		(0x1 << 20)

#define		ATC_DCSIZE_8		(0x2 << 20)

#define		ATC_DCSIZE_16		(0x3 << 20)

#define		ATC_DCSIZE_32		(0x4 << 20)

#define		ATC_DCSIZE_64		(0x5 << 20)

#define		ATC_DCSIZE_128		(0x6 << 20)

#define		ATC_DCSIZE_256		(0x7 << 20)



#endif /* AT_HDMAC_H */

drivers/dma/at_hdmac.c

+4 −3
Original line number Diff line number Diff line
@@ -666,7 +666,8 @@ atc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, 
		return NULL;

	}



	ctrla = atslave->ctrla;

	ctrla =   ATC_SCSIZE(sconfig->src_maxburst)

		| ATC_DCSIZE(sconfig->dst_maxburst);

	ctrlb = ATC_IEN;



	switch (direction) {
@@ -794,12 +795,12 @@ atc_dma_cyclic_fill_desc(struct dma_chan *chan, struct at_desc *desc, 
		enum dma_transfer_direction direction)

{

	struct at_dma_chan	*atchan = to_at_dma_chan(chan);

	struct at_dma_slave	*atslave = chan->private;

	struct dma_slave_config	*sconfig = &atchan->dma_sconfig;

	u32			ctrla;



	/* prepare common CRTLA value */

	ctrla = atslave->ctrla

	ctrla =   ATC_SCSIZE(sconfig->src_maxburst)

		| ATC_DCSIZE(sconfig->dst_maxburst)

		| ATC_DST_WIDTH(reg_width)

		| ATC_SRC_WIDTH(reg_width)

		| period_len >> reg_width;

drivers/dma/at_hdmac_regs.h

+20 −1
Original line number Diff line number Diff line
@@ -87,7 +87,26 @@ 
/* Bitfields in CTRLA */

#define	ATC_BTSIZE_MAX		0xFFFFUL	/* Maximum Buffer Transfer Size */

#define	ATC_BTSIZE(x)		(ATC_BTSIZE_MAX & (x)) /* Buffer Transfer Size */

/* Chunck Tranfer size definitions are in at_hdmac.h */

#define	ATC_SCSIZE_MASK		(0x7 << 16)	/* Source Chunk Transfer Size */

#define		ATC_SCSIZE(x)		(ATC_SCSIZE_MASK & ((x) << 16))

#define		ATC_SCSIZE_1		(0x0 << 16)

#define		ATC_SCSIZE_4		(0x1 << 16)

#define		ATC_SCSIZE_8		(0x2 << 16)

#define		ATC_SCSIZE_16		(0x3 << 16)

#define		ATC_SCSIZE_32		(0x4 << 16)

#define		ATC_SCSIZE_64		(0x5 << 16)

#define		ATC_SCSIZE_128		(0x6 << 16)

#define		ATC_SCSIZE_256		(0x7 << 16)

#define	ATC_DCSIZE_MASK		(0x7 << 20)	/* Destination Chunk Transfer Size */

#define		ATC_DCSIZE(x)		(ATC_DCSIZE_MASK & ((x) << 20))

#define		ATC_DCSIZE_1		(0x0 << 20)

#define		ATC_DCSIZE_4		(0x1 << 20)

#define		ATC_DCSIZE_8		(0x2 << 20)

#define		ATC_DCSIZE_16		(0x3 << 20)

#define		ATC_DCSIZE_32		(0x4 << 20)

#define		ATC_DCSIZE_64		(0x5 << 20)

#define		ATC_DCSIZE_128		(0x6 << 20)

#define		ATC_DCSIZE_256		(0x7 << 20)

#define	ATC_SRC_WIDTH_MASK	(0x3 << 24)	/* Source Single Transfer Size */

#define		ATC_SRC_WIDTH(x)	((x) << 24)

#define		ATC_SRC_WIDTH_BYTE	(0x0 << 24)