Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 1d487f46 authored by Bryan Wu's avatar Bryan Wu
Browse files

Blackfin arch: add TWIx_REGBASE and SPIx_REGBASE to specific CPU header files,... 


Blackfin arch: add TWIx_REGBASE and SPIx_REGBASE to specific CPU header files, use the new REGBASE for board platform resources

Signed-off-by: default avatarBryan Wu <bryan.wu@analog.com>
parent b7b2d344

include/asm-blackfin/bfin5xx_spi.h

+0 −2
Original line number Diff line number Diff line
@@ -21,8 +21,6 @@ 
#ifndef _SPI_CHANNEL_H_

#define _SPI_CHANNEL_H_



#define SPI0_REGBASE       0xffc00500



#define SPI_READ              0

#define SPI_WRITE             1

include/asm-blackfin/mach-bf527/defBF52x_base.h

+2 −0
Original line number Diff line number Diff line
@@ -102,6 +102,7 @@ 




/* SPI Controller			(0xFFC00500 - 0xFFC005FF)								*/

#define SPI0_REGBASE			0xFFC00500

#define SPI_CTL				0xFFC00500	/* SPI Control Register						*/

#define SPI_FLG				0xFFC00504	/* SPI Flag register						*/

#define SPI_STAT			0xFFC00508	/* SPI Status register						*/
@@ -480,6 +481,7 @@ 




/* Two-Wire Interface		(0xFFC01400 - 0xFFC014FF)								*/

#define TWI0_REGBASE			0xFFC01400

#define TWI_CLKDIV			0xFFC01400	/* Serial Clock Divider Register			*/

#define TWI_CONTROL			0xFFC01404	/* TWI Control Register						*/

#define TWI_SLAVE_CTL		0xFFC01408	/* Slave Mode Control Register				*/

include/asm-blackfin/mach-bf533/defBF532.h

+1 −0
Original line number Diff line number Diff line
@@ -104,6 +104,7 @@ 
#define UART_GCTL      	      		 0xFFC00424	/* Global Control Register */



/* SPI Controller (0xFFC00500 - 0xFFC005FF) */

#define SPI0_REGBASE          		0xFFC00500

#define SPI_CTL               		0xFFC00500	/* SPI Control Register */

#define SPI_FLG               		0xFFC00504	/* SPI Flag register */

#define SPI_STAT              		0xFFC00508	/* SPI Status register */

include/asm-blackfin/mach-bf537/defBF534.h

+2 −0
Original line number Diff line number Diff line
@@ -86,6 +86,7 @@ 
#define UART0_GCTL			0xFFC00424	/* Global Control Register                                      */



/* SPI Controller			(0xFFC00500 - 0xFFC005FF)								*/

#define SPI0_REGBASE			0xFFC00500

#define SPI_CTL				0xFFC00500	/* SPI Control Register                                         */

#define SPI_FLG				0xFFC00504	/* SPI Flag register                                            */

#define SPI_STAT			0xFFC00508	/* SPI Status register                                          */
@@ -456,6 +457,7 @@ 
#define PPI_FRAME			0xFFC01010	/* PPI Frame Length Register    */



/* Two-Wire Interface		(0xFFC01400 - 0xFFC014FF)								*/

#define TWI0_REGBASE			0xFFC01400

#define TWI_CLKDIV			0xFFC01400	/* Serial Clock Divider Register                        */

#define TWI_CONTROL			0xFFC01404	/* TWI Control Register                                         */

#define TWI_SLAVE_CTL		0xFFC01408	/* Slave Mode Control Register                          */

include/asm-blackfin/mach-bf548/defBF544.h

+1 −0
Original line number Diff line number Diff line
@@ -81,6 +81,7 @@ 


/* Two Wire Interface Registers (TWI1) */



#define                     TWI1_REGBASE  0xffc02200

#define                      TWI1_CLKDIV  0xffc02200   /* Clock Divider Register */

#define                     TWI1_CONTROL  0xffc02204   /* TWI Control Register */

#define                  TWI1_SLAVE_CTRL  0xffc02208   /* TWI Slave Mode Control Register */