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Commit 1d2866ba authored by Ben Widawsky's avatar Ben Widawsky Committed by Daniel Vetter
Browse files

drm/i915/bdw: enable eDRAM. 



The same register exists for querying and programming eDRAM AKA eLLC. So
we can simply use it. For now, use all the same defaults as we had
for Haswell, since like Haswell, I have no further details.

I do not actually have a part with eDRAM, so I cannot test this.

Signed-off-by: default avatarBen Widawsky <ben@bwidawsk.net>
Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@gmail.com>
Reviewed-by: default avatarBrad Volkin <bradley.d.volkin@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 63c42e56

drivers/gpu/drm/i915/intel_uncore.c

+1 −1
Original line number Diff line number Diff line
@@ -370,7 +370,7 @@ void intel_uncore_early_sanitize(struct drm_device *dev) 
	if (HAS_FPGA_DBG_UNCLAIMED(dev))

		__raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);



	if (IS_HASWELL(dev) &&

	if ((IS_HASWELL(dev) || IS_BROADWELL(dev)) &&

	    (__raw_i915_read32(dev_priv, HSW_EDRAM_PRESENT) == 1)) {

		/* The docs do not explain exactly how the calculation can be

		 * made. It is somewhat guessable, but for now, it's always