Loading soc/swr-mstr-ctrl.c +17 −1 Original line number Diff line number Diff line Loading @@ -2988,7 +2988,23 @@ static int swrm_runtime_suspend(struct device *dev) mutex_unlock(&swrm->reslock); enable_bank_switch(swrm, 0, SWR_ROW_50, SWR_MIN_COL); mutex_lock(&swrm->reslock); if (!swrm->clk_stop_mode0_supp) { swrm_clk_pause(swrm); } else { /* Mask bus clash interrupt */ swrm->intr_mask &= ~((u32)0x08); swr_master_write(swrm, SWRM_INTERRUPT_MASK_ADDR, swrm->intr_mask); swr_master_write(swrm, SWR_MSTR_RX_SWRM_CPU_INTERRUPT_EN, swrm->intr_mask); mutex_unlock(&swrm->reslock); /* clock stop sequence */ swrm_cmd_fifo_wr_cmd(swrm, 0x2, 0xF, 0xF, SWRS_SCP_CONTROL); mutex_lock(&swrm->reslock); } swr_master_write(swrm, SWRM_COMP_CFG_ADDR, 0x00); list_for_each_entry(swr_dev, &mstr->devices, dev_list) { ret = swr_device_down(swr_dev); Loading Loading
soc/swr-mstr-ctrl.c +17 −1 Original line number Diff line number Diff line Loading @@ -2988,7 +2988,23 @@ static int swrm_runtime_suspend(struct device *dev) mutex_unlock(&swrm->reslock); enable_bank_switch(swrm, 0, SWR_ROW_50, SWR_MIN_COL); mutex_lock(&swrm->reslock); if (!swrm->clk_stop_mode0_supp) { swrm_clk_pause(swrm); } else { /* Mask bus clash interrupt */ swrm->intr_mask &= ~((u32)0x08); swr_master_write(swrm, SWRM_INTERRUPT_MASK_ADDR, swrm->intr_mask); swr_master_write(swrm, SWR_MSTR_RX_SWRM_CPU_INTERRUPT_EN, swrm->intr_mask); mutex_unlock(&swrm->reslock); /* clock stop sequence */ swrm_cmd_fifo_wr_cmd(swrm, 0x2, 0xF, 0xF, SWRS_SCP_CONTROL); mutex_lock(&swrm->reslock); } swr_master_write(swrm, SWRM_COMP_CFG_ADDR, 0x00); list_for_each_entry(swr_dev, &mstr->devices, dev_list) { ret = swr_device_down(swr_dev); Loading