usb: dwc3: clean up whitespace damage, typos, missing parens, etc.

}

/**

 * dwc3_alloc_one_event_buffer - Allocated one event buffer structure

 * dwc3_alloc_one_event_buffer - Allocates one event buffer structure

 * @dwc: Pointer to our controller context structure

 * @length: size of the event buffer

 *

 * Returns a pointer to the allocated event buffer structure on succes

 * Returns a pointer to the allocated event buffer structure on success

 * otherwise ERR_PTR(errno).

 */

static struct dwc3_event_buffer *__devinit

/**

 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length

 * @dwc: Pointer to out controller context structure

 * @dwc: pointer to our controller context structure

 * @length: size of event buffer

 *

 * Returns 0 on success otherwise negative errno. In error the case, dwc

 * Returns 0 on success otherwise negative errno. In the error case, dwc

 * may contain some buffers allocated but not all which were requested.

 */

static int __devinit dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)

/**

 * dwc3_event_buffers_setup - setup our allocated event buffers

 * @dwc: Pointer to out controller context structure

 * @dwc: pointer to our controller context structure

 *

 * Returns 0 on success otherwise negative errno.

 */

	/*

	 * WORKAROUND: DWC3 revisions <1.90a have a bug

	 * when The device fails to connect at SuperSpeed

	 * where the device can fail to connect at SuperSpeed

	 * and falls back to high-speed mode which causes

	 * the device to enter in a Connect/Disconnect loop

	 * the device to enter a Connect/Disconnect loop

	 */

	if (dwc->revision < DWC3_REVISION_190A)

		reg |= DWC3_GCTL_U2RSTECN;

/* Bit fields */

/* Global Configuration Register */

#define DWC3_GCTL_PWRDNSCALE(n)	(n << 19)

#define DWC3_GCTL_PWRDNSCALE(n)	((n) << 19)

#define DWC3_GCTL_U2RSTECN	(1 << 16)

#define DWC3_GCTL_RAMCLKSEL(x)	((x & DWC3_GCTL_CLK_MASK) << 6)

#define DWC3_GCTL_RAMCLKSEL(x)	(((x) & DWC3_GCTL_CLK_MASK) << 6)

#define DWC3_GCTL_CLK_BUS	(0)

#define DWC3_GCTL_CLK_PIPE	(1)

#define DWC3_GCTL_CLK_PIPEHALF	(2)

#define DWC3_GCTL_CLK_MASK	(3)

#define DWC3_GCTL_PRTCAP(n)	(((n) & (3 << 12)) >> 12)

#define DWC3_GCTL_PRTCAPDIR(n)	(n << 12)

#define DWC3_GCTL_PRTCAPDIR(n)	((n) << 12)

#define DWC3_GCTL_PRTCAP_HOST	1

#define DWC3_GCTL_PRTCAP_DEVICE	2

#define DWC3_GCTL_PRTCAP_OTG	3

#define DWC3_GCTL_CORESOFTRESET	(1 << 11)

#define DWC3_GCTL_SCALEDOWN(n)	(n << 4)

#define DWC3_GCTL_SCALEDOWN(n)	((n) << 4)

#define DWC3_GCTL_DISSCRAMBLE	(1 << 3)

#define DWC3_GCTL_DSBLCLKGTNG	(1 << 0)

#define DWC3_GTXFIFOSIZ_TXFSTADDR(n) ((n) & 0xffff0000)

/* Global HWPARAMS1 Register */

#define DWC3_GHWPARAMS1_EN_PWROPT(n)	((n & (3 << 24)) >> 24)

#define DWC3_GHWPARAMS1_EN_PWROPT(n)	(((n) & (3 << 24)) >> 24)

#define DWC3_GHWPARAMS1_EN_PWROPT_NO	0

#define DWC3_GHWPARAMS1_EN_PWROPT_CLK	1

/* Device Endpoint Command Register */

#define DWC3_DEPCMD_PARAM_SHIFT		16

#define DWC3_DEPCMD_PARAM(x)		(x << DWC3_DEPCMD_PARAM_SHIFT)

#define DWC3_DEPCMD_GET_RSC_IDX(x)	((x >> DWC3_DEPCMD_PARAM_SHIFT) & 0x7f)

#define DWC3_DEPCMD_PARAM(x)		((x) << DWC3_DEPCMD_PARAM_SHIFT)

#define DWC3_DEPCMD_GET_RSC_IDX(x)     (((x) >> DWC3_DEPCMD_PARAM_SHIFT) & 0x7f)

#define DWC3_DEPCMD_STATUS_MASK		(0x0f << 12)

#define DWC3_DEPCMD_STATUS(x)		((x & DWC3_DEPCMD_STATUS_MASK) >> 12)

#define DWC3_DEPCMD_STATUS(x)		(((x) & DWC3_DEPCMD_STATUS_MASK) >> 12)

#define DWC3_DEPCMD_HIPRI_FORCERM	(1 << 11)

#define DWC3_DEPCMD_CMDACT		(1 << 10)

#define DWC3_DEPCMD_CMDIOC		(1 << 8)

		memset(&trb_link, 0, sizeof(trb_link));

		/* Link TRB for ISOC. The HWO but is never reset */

		/* Link TRB for ISOC. The HWO bit is never reset */

		trb_st_hw = &dep->trb_pool[0];

		trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];

 * @dep: endpoint for which requests are being prepared

 * @starting: true if the endpoint is idle and no requests are queued.

 *

 * The functions goes through the requests list and setups TRBs for the

 * transfers. The functions returns once there are not more TRBs available or

 * it run out of requests.

 * The function goes through the requests list and sets up TRBs for the

 * transfers. The function returns once there are no more TRBs available or

 * it runs out of requests.

 */

static void dwc3_prepare_trbs(struct dwc3_ep *dep, bool starting)

{

	trbs_left = (dep->busy_slot - dep->free_slot) & DWC3_TRB_MASK;

	/*

	 * if busy & slot are equal than it is either full or empty. If we are

	 * starting to proceed requests then we are empty. Otherwise we ar

	 * If busy & slot are equal than it is either full or empty. If we are

	 * starting to process requests then we are empty. Otherwise we are

	 * full and don't do anything

	 */

	if (!trbs_left) {

		 * In case we start from scratch, we queue the ISOC requests

		 * starting from slot 1. This is done because we use ring

		 * buffer and have no LST bit to stop us. Instead, we place

		 * IOC bit TRB_NUM/4. We try to avoid to having an interrupt

		 * IOC bit every TRB_NUM/4. We try to avoid having an interrupt

		 * after the first request so we start at slot 1 and have

		 * 7 requests proceed before we hit the first IOC.

		 * Other transfer types don't use the ring buffer and are

				length = sg_dma_len(s);

				dma = sg_dma_address(s);

				if (i == (request->num_mapped_sgs - 1)

						|| sg_is_last(s)) {

				if (i == (request->num_mapped_sgs - 1) ||

						sg_is_last(s)) {

					last_one = true;

					chain = false;

				}

		dwc3_prepare_trbs(dep, start_new);

		/*

		 * req points to the first request where HWO changed

		 * from 0 to 1

		 * req points to the first request where HWO changed from 0 to 1

		 */

		req = next_request(&dep->req_queued);

	}

		/*

		 * FIXME we need to iterate over the list of requests

		 * here and stop, unmap, free and del each of the linked

		 * requests instead of we do now.

		 * requests instead of what we do now.

		 */

		dwc3_unmap_buffer_from_dma(req);

		list_del(&req->list);

	 * particular token from the Host side.

	 *

	 * This will also avoid Host cancelling URBs due to too

	 * many NACKs.

	 * many NAKs.

	 */

	dwc3_map_buffer_to_dma(req);

	list_add_tail(&req->list, &dep->request_list);

		start_trans = 1;

		if (usb_endpoint_xfer_isoc(dep->desc) &&

				dep->flags & DWC3_EP_BUSY)

				(dep->flags & DWC3_EP_BUSY))

			start_trans = 0;

		ret = __dwc3_gadget_kick_transfer(dep, 0, start_trans);

	reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;

	dwc3_writel(dwc->regs, DWC3_DCTL, reg);

	/* pool until Link State change to ON */

	/* poll until Link State changes to ON */

	timeout = jiffies + msecs_to_jiffies(100);

	while (!(time_after(jiffies, timeout))) {

	while (!time_after(jiffies, timeout)) {

		reg = dwc3_readl(dwc->regs, DWC3_DSTS);

		/* in HS, means ON */

		if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)

			/*

			 * We continue despite the error. There is not much we

			 * can do. If we don't clean in up we loop for ever. If

			 * we skip the TRB than it gets overwritten reused after

			 * a while since we use them in a ring buffer. a BUG()

			 * would help. Lets hope that if this occures, someone

			 * can do. If we don't clean it up we loop forever. If

			 * we skip the TRB then it gets overwritten after a

			 * while since we use them in a ring buffer. A BUG()

			 * would help. Lets hope that if this occurs, someone

			 * fixes the root cause instead of looking away :)

			 */

			dev_err(dwc->dev, "%s's TRB (%p) still owned by HW\n",

	struct dwc3_event_depevt mod_ev = *event;

	/*

	 * We were asked to remove one requests. It is possible that this

	 * request and a few other were started together and have the same

	 * We were asked to remove one request. It is possible that this

	 * request and a few others were started together and have the same

	 * transfer index. Since we stopped the complete endpoint we don't

	 * know how many requests were already completed (and not yet)

	 * reported and how could be done (later). We purge them all until

	mod_ev.status = DEPEVT_STATUS_LST;

	dwc3_cleanup_done_reqs(dwc, dep, &mod_ev, -ESHUTDOWN);

	dep->flags &= ~DWC3_EP_BUSY;

	/* pending requets are ignored and are queued on XferNotReady */

	/* pending requests are ignored and are queued on XferNotReady */

}

static void dwc3_ep_cmd_compl(struct dwc3_ep *dep,

/**

 * dwc3_gadget_init - Initializes gadget related registers

 * @dwc: Pointer to out controller context structure

 * @dwc: pointer to our controller context structure

 *

 * Returns 0 on success otherwise negative errno.

 */