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Commit 1ca81150 authored by Jernej Skrabec's avatar Jernej Skrabec Committed by Greg Kroah-Hartman
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drm/sun4i: Fix sun8i HDMI PHY configuration for > 148.5 MHz 



commit 831adffb3b7b8df4c8e20b7b00843129fb87a166 upstream.

Vendor provided documentation says that EMP bits should be set to 3 for
pixel clocks greater than 148.5 MHz.

Fix that.

Cc: stable@vger.kernel.org # 4.17+
Fixes: 4f86e817 ("drm/sun4i: Add support for H3 HDMI PHY variant")
Signed-off-by: default avatarJernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: default avatarMaxime Ripard <maxime.ripard@bootlin.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190514204337.11068-3-jernej.skrabec@siol.net


Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 1f137220

drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c

+2 −1
Original line number Diff line number Diff line
@@ -177,7 +177,8 @@ static int sun8i_hdmi_phy_config_h3(struct dw_hdmi *hdmi, 
				 SUN8I_HDMI_PHY_ANA_CFG2_REG_BIGSW |

				 SUN8I_HDMI_PHY_ANA_CFG2_REG_SLV(4);

		ana_cfg3_init |= SUN8I_HDMI_PHY_ANA_CFG3_REG_AMPCK(9) |

				 SUN8I_HDMI_PHY_ANA_CFG3_REG_AMP(13);

				 SUN8I_HDMI_PHY_ANA_CFG3_REG_AMP(13) |

				 SUN8I_HDMI_PHY_ANA_CFG3_REG_EMP(3);

	}



	regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG,