Merge airlied/drm-next into drm-misc-next

Renesas R-Car LVDS Encoder

==========================

These DT bindings describe the LVDS encoder embedded in the Renesas R-Car

Gen2, R-Car Gen3 and RZ/G SoCs.

Required properties:

- compatible : Shall contain one of

  - "renesas,r8a7743-lvds" for R8A7743 (RZ/G1M) compatible LVDS encoders

  - "renesas,r8a7790-lvds" for R8A7790 (R-Car H2) compatible LVDS encoders

  - "renesas,r8a7791-lvds" for R8A7791 (R-Car M2-W) compatible LVDS encoders

  - "renesas,r8a7793-lvds" for R8A7793 (R-Car M2-N) compatible LVDS encoders

  - "renesas,r8a7795-lvds" for R8A7795 (R-Car H3) compatible LVDS encoders

  - "renesas,r8a7796-lvds" for R8A7796 (R-Car M3-W) compatible LVDS encoders

  - "renesas,r8a77970-lvds" for R8A77970 (R-Car V3M) compatible LVDS encoders

  - "renesas,r8a77995-lvds" for R8A77995 (R-Car D3) compatible LVDS encoders

- reg: Base address and length for the memory-mapped registers

- clocks: A phandle + clock-specifier pair for the functional clock

- resets: A phandle + reset specifier for the module reset

Required nodes:

The LVDS encoder has two video ports. Their connections are modelled using the

OF graph bindings specified in Documentation/devicetree/bindings/graph.txt.

- Video port 0 corresponds to the parallel RGB input

- Video port 1 corresponds to the LVDS output

Each port shall have a single endpoint.

Example:

	lvds0: lvds@feb90000 {

		compatible = "renesas,r8a7790-lvds";

		reg = <0 0xfeb90000 0 0x1c>;

		clocks = <&cpg CPG_MOD 726>;

		resets = <&cpg 726>;

		ports {

			#address-cells = <1>;

			#size-cells = <0>;

			port@0 {

				reg = <0>;

				lvds0_in: endpoint {

					remote-endpoint = <&du_out_lvds0>;

				};

			};

			port@1 {

				reg = <1>;

				lvds0_out: endpoint {

				};

			};

		};

	};

- analog: the connector has DVI analog pins

- digital: the connector has DVI digital pins

- dual-link: the connector has pins for DVI dual-link

- hpd-gpios: HPD GPIO number

Required nodes:

- Video port for DVI input

- reg: Physical base address and length of the registers of controller

- reg-names: The names of register regions. The following regions are required:

  * "dsi_ctrl"

- qcom,dsi-host-index: The ID of DSI controller hardware instance. This should

  be 0 or 1, since we have 2 DSI controllers at most for now.

- interrupts: The interrupt signal from the DSI block.

- power-domains: Should be <&mmcc MDSS_GDSC>.

- clocks: Phandles to device clocks.

  * "core"

  For DSIv2, we need an additional clock:

   * "src"

  For DSI6G v2.0 onwards, we need also need the clock:

   * "byte_intf"

- assigned-clocks: Parents of "byte" and "pixel" for the given platform.

- assigned-clock-parents: The Byte clock and Pixel clock PLL outputs provided

  by a DSI PHY block. See [1] for details on clock bindings.

  * "qcom,dsi-phy-28nm-lp"

  * "qcom,dsi-phy-20nm"

  * "qcom,dsi-phy-28nm-8960"

- reg: Physical base address and length of the registers of PLL, PHY and PHY

  regulator

  * "qcom,dsi-phy-14nm"

  * "qcom,dsi-phy-10nm"

- reg: Physical base address and length of the registers of PLL, PHY. Some

  revisions require the PHY regulator base address, whereas others require the

  PHY lane base address. See below for each PHY revision.

- reg-names: The names of register regions. The following regions are required:

  For DSI 28nm HPM/LP/8960 PHYs and 20nm PHY:

  * "dsi_pll"

  * "dsi_phy"

  * "dsi_phy_regulator"

  For DSI 14nm and 10nm PHYs:

  * "dsi_pll"

  * "dsi_phy"

  * "dsi_phy_lane"

- clock-cells: Must be 1. The DSI PHY block acts as a clock provider, creating

  2 clocks: A byte clock (index 0), and a pixel clock (index 1).

- qcom,dsi-phy-index: The ID of DSI PHY hardware instance. This should

  be 0 or 1, since we have 2 DSI PHYs at most for now.

- power-domains: Should be <&mmcc MDSS_GDSC>.

- clocks: Phandles to device clocks. See [1] for details on clock bindings.

- clock-names: the following clocks are required:

  * "iface"

  For 28nm HPM/LP, 28nm 8960 PHYs:

- vddio-supply: phandle to vdd-io regulator device node

  For 20nm PHY:

- vddio-supply: phandle to vdd-io regulator device node

- vcca-supply: phandle to vcca regulator device node

  For 14nm PHY:

- vcca-supply: phandle to vcca regulator device node

  For 10nm PHY:

- vdds-supply: phandle to vdds regulator device node

Optional properties:

- qcom,dsi-phy-regulator-ldo-mode: Boolean value indicating if the LDO mode PHY

    - "renesas,du-r8a7794" for R8A7794 (R-Car E2) compatible DU

    - "renesas,du-r8a7795" for R8A7795 (R-Car H3) compatible DU

    - "renesas,du-r8a7796" for R8A7796 (R-Car M3-W) compatible DU

    - "renesas,du-r8a77970" for R8A77970 (R-Car V3M) compatible DU

    - "renesas,du-r8a77995" for R8A77995 (R-Car D3) compatible DU

  - reg: A list of base address and length of each memory resource, one for

    each entry in the reg-names property.

  - reg-names: Name of the memory resources. The DU requires one memory

    resource for the DU core (named "du") and one memory resource for each

    LVDS encoder (named "lvds.x" with "x" being the LVDS controller numerical

    index).

  - reg: the memory-mapped I/O registers base address and length

  - interrupt-parent: phandle of the parent interrupt controller.

  - interrupts: Interrupt specifiers for the DU interrupts.

  - clock-names: Name of the clocks. This property is model-dependent.

    - R8A7779 uses a single functional clock. The clock doesn't need to be

      named.

    - All other DU instances use one functional clock per channel and one

      clock per LVDS encoder (if available). The functional clocks must be

      named "du.x" with "x" being the channel numerical index. The LVDS clocks

      must be named "lvds.x" with "x" being the LVDS encoder numerical index.

    - In addition to the functional and encoder clocks, all DU versions also

      support externally supplied pixel clocks. Those clocks are optional.

      When supplied they must be named "dclkin.x" with "x" being the input

      clock numerical index.

    - All other DU instances use one functional clock per channel The

      functional clocks must be named "du.x" with "x" being the channel

      numerical index.

    - In addition to the functional clocks, all DU versions also support

      externally supplied pixel clocks. Those clocks are optional. When

      supplied they must be named "dclkin.x" with "x" being the input clock

      numerical index.

  - vsps: A list of phandle and channel index tuples to the VSPs that handle

    the memory interfaces for the DU channels. The phandle identifies the VSP

 R8A7794 (R-Car E2)   DPAD 0         DPAD 1         -              -

 R8A7795 (R-Car H3)   DPAD 0         HDMI 0         HDMI 1         LVDS 0

 R8A7796 (R-Car M3-W) DPAD 0         HDMI 0         LVDS 0         -

 R8A77970 (R-Car V3M) DPAD 0         LVDS 0         -              -

 R8A77995 (R-Car D3)  DPAD 0         LVDS 0         LVDS 1         -

Example: R8A7795 (R-Car H3) ES2.0 DU

	du: display@feb00000 {

		compatible = "renesas,du-r8a7795";

		reg = <0 0xfeb00000 0 0x80000>,

		      <0 0xfeb90000 0 0x14>;

		reg-names = "du", "lvds.0";

		reg = <0 0xfeb00000 0 0x80000>;

		interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,

		clocks = <&cpg CPG_MOD 724>,

			 <&cpg CPG_MOD 723>,

			 <&cpg CPG_MOD 722>,

			 <&cpg CPG_MOD 721>,

			 <&cpg CPG_MOD 727>;

		clock-names = "du.0", "du.1", "du.2", "du.3", "lvds.0";

			 <&cpg CPG_MOD 721>;

		clock-names = "du.0", "du.1", "du.2", "du.3";

		vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>, <&vspd0 1>;

		ports {

The API is quite easy to use.

1. Call of_overlay_apply() to create and apply an overlay changeset. The return

value is an error or a cookie identifying this overlay.

1. Call of_overlay_fdt_apply() to create and apply an overlay changeset. The

return value is an error or a cookie identifying this overlay.

2. Call of_overlay_remove() to remove and cleanup the overlay changeset

previously created via the call to of_overlay_apply(). Removal of an overlay