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Commit 1c4a0437 authored by Umang Agrawal's avatar Umang Agrawal Committed by Guru Das Srinagesh
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power: smb5: Evaluate step charging on wdog snarl 



Currently, step charging flow is evaluated on every wdog bark irq
trigger. However, the minimum frequency of wdog bark can be 16sec only.
This prevents close approximation of tapered down step-charging
to CC1->CV1->CC2->CV2 mode. Hence, add support to evaluate step charging
flow on every wdog snarl irq, which can trigger at a frequency of 1s,
2s, 4s and 8s, allowing for better approximation.

Further, as per current SW design, wodg snarl IRQ is enabled only if SW
thermal regulation WA is active. To enable wdog snarl irq explicitly for
step charging, its required to specify snarl timer configuration as a dt
parameter. Henceforth, if either wdog snarl timer configuration is defined
as a dt parameter or SW thermal regulation WA is active, then only wdog
snarl irq is enabled, else disabled by default.

Change-Id: I243a23608123ede11c5d497618091cb044203e49
Signed-off-by: default avatarUmang Agrawal <uagrawal@codeaurora.org>
Signed-off-by: default avatarGuru Das Srinagesh <gurus@codeaurora.org>
parent 705d34f7

drivers/power/supply/qcom/qpnp-smb5.c

+21 −6
Original line number Diff line number Diff line
@@ -210,6 +210,7 @@ struct smb_dt_props { 
	int			auto_recharge_soc;

	int			auto_recharge_vbat_mv;

	int			wd_bark_time;

	int			wd_snarl_time_cfg;

	int			batt_profile_fcc_ua;

	int			batt_profile_fv_uv;

	int			term_current_src;
@@ -448,6 +449,11 @@ static int smb5_parse_dt_misc(struct smb5 *chip, struct device_node *node) 
	if (rc < 0 || chip->dt.wd_bark_time < MIN_WD_BARK_TIME)

		chip->dt.wd_bark_time = DEFAULT_WD_BARK_TIME;



	rc = of_property_read_u32(node, "qcom,wd-snarl-time-config",

					&chip->dt.wd_snarl_time_cfg);

	if (rc < 0)

		chip->dt.wd_snarl_time_cfg = -EINVAL;



	chip->dt.no_battery = of_property_read_bool(node,

						"qcom,batteryless-platform");
@@ -2454,9 +2460,17 @@ static int smb5_init_hw(struct smb5 *chip) 
	val = (ilog2(chip->dt.wd_bark_time / 16) << BARK_WDOG_TIMEOUT_SHIFT)

			& BARK_WDOG_TIMEOUT_MASK;

	val |= (BITE_WDOG_TIMEOUT_8S | BITE_WDOG_DISABLE_CHARGING_CFG_BIT);



	if (chip->dt.wd_snarl_time_cfg == -EINVAL)

		val |= SNARL_WDOG_TMOUT_8S;

	else

		val |= (chip->dt.wd_snarl_time_cfg << SNARL_WDOG_TIMEOUT_SHIFT)

			& SNARL_WDOG_TIMEOUT_MASK;



	rc = smblib_masked_write(chg, SNARL_BARK_BITE_WD_CFG_REG,

			BITE_WDOG_DISABLE_CHARGING_CFG_BIT |

			BARK_WDOG_TIMEOUT_MASK | BITE_WDOG_TIMEOUT_MASK,

			SNARL_WDOG_TIMEOUT_MASK | BARK_WDOG_TIMEOUT_MASK |

			BITE_WDOG_TIMEOUT_MASK,

			val);

	if (rc < 0) {

		pr_err("Couldn't configue WD config rc=%d\n", rc);
@@ -2960,13 +2974,14 @@ static int smb5_request_interrupts(struct smb5 *chip) 
		chg->usb_icl_change_irq_enabled = true;



	/*

	 * WDOG_SNARL_IRQ is required for SW Thermal Regulation WA only. In

	 * case the WA is not required, disable the WDOG_SNARL_IRQ to prevent

	 * interrupt storm.

	 * WDOG_SNARL_IRQ is required for SW Thermal Regulation WA. In case

	 * the WA is not required and neither is the snarl timer configuration

	 * defined, disable the WDOG_SNARL_IRQ to prevent interrupt storm.

	 */



	if (chg->irq_info[WDOG_SNARL_IRQ].irq && !(chg->wa_flags &

						SW_THERM_REGULATION_WA)) {

	if (chg->irq_info[WDOG_SNARL_IRQ].irq && (!(chg->wa_flags &

				SW_THERM_REGULATION_WA) &&

				chip->dt.wd_snarl_time_cfg == -EINVAL)) {

		disable_irq_wake(chg->irq_info[WDOG_SNARL_IRQ].irq);

		disable_irq_nosync(chg->irq_info[WDOG_SNARL_IRQ].irq);

	}

drivers/power/supply/qcom/smb5-lib.c

+3 −0
Original line number Diff line number Diff line
@@ -5628,6 +5628,9 @@ irqreturn_t wdog_snarl_irq_handler(int irq, void *data) 
		schedule_delayed_work(&chg->thermal_regulation_work, 0);

	}



	if (chg->step_chg_enabled)

		power_supply_changed(chg->batt_psy);



	return IRQ_HANDLED;

}

drivers/power/supply/qcom/smb5-reg.h

+1 −0
Original line number Diff line number Diff line
@@ -488,6 +488,7 @@ enum { 
#define SNARL_BARK_BITE_WD_CFG_REG		(MISC_BASE + 0x53)

#define BITE_WDOG_DISABLE_CHARGING_CFG_BIT	BIT(7)

#define SNARL_WDOG_TIMEOUT_MASK                 GENMASK(6, 4)

#define SNARL_WDOG_TIMEOUT_SHIFT		4

#define SNARL_WDOG_TMOUT_62P5MS			0x00

#define SNARL_WDOG_TMOUT_1S			0x40

#define SNARL_WDOG_TMOUT_8S			0x70