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Commit 1c41b61f authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "disp: msm: dp: check HDMI max tmds clock when setting bpp"

parents 86fa8f9f 0f4f1114

msm/dp/dp_display.c

+13 −1
Original line number Diff line number Diff line
@@ -1657,6 +1657,11 @@ static int dp_display_set_mode(struct dp_display *dp_display, void *panel, 
	dp = container_of(dp_display, struct dp_display_private, dp_display);



	mutex_lock(&dp->session_lock);



	if (dp_panel->connector->display_info.max_tmds_clock > 0)

		dp->panel->connector->display_info.max_tmds_clock =

			dp_panel->connector->display_info.max_tmds_clock;



	mode->timing.bpp =

		dp_panel->connector->display_info.bpc * num_components;

	if (!mode->timing.bpp)
@@ -2134,7 +2139,7 @@ static enum drm_mode_status dp_display_validate_mode( 
	struct dp_display_mode dp_mode;

	bool dsc_en;

	u32 num_lm = 0;

	int rc = 0;

	int rc = 0, tmds_max_clock = 0;



	if (!dp_display || !mode || !panel ||

			!avail_res || !avail_res->max_mixer_width) {
@@ -2167,6 +2172,7 @@ static enum drm_mode_status dp_display_validate_mode( 
	mode_rate_khz = mode->clock * mode_bpp;

	rate = drm_dp_bw_code_to_link_rate(dp->link->link_params.bw_code);

	supported_rate_khz = link_info->num_lanes * rate * 8;

	tmds_max_clock = dp_panel->connector->display_info.max_tmds_clock;



	if (mode_rate_khz > supported_rate_khz) {

		DP_MST_DEBUG("pclk:%d, supported_rate:%d\n",
@@ -2180,6 +2186,12 @@ static enum drm_mode_status dp_display_validate_mode( 
		goto end;

	}



	if (tmds_max_clock > 0 && mode->clock > tmds_max_clock) {

		DP_MST_DEBUG("clk:%d, max tmds:%d\n", mode->clock,

				tmds_max_clock);

		goto end;

	}



	rc = msm_get_mixer_count(dp->priv, mode, avail_res, &num_lm);

	if (rc) {

		DP_ERR("error getting mixer count. rc:%d\n", rc);

msm/dp/dp_panel.c

+6 −1
Original line number Diff line number Diff line
@@ -2174,7 +2174,7 @@ static u32 dp_panel_get_supported_bpp(struct dp_panel *dp_panel, 
	struct drm_dp_link *link_info;

	const u32 max_supported_bpp = 30;

	u32 min_supported_bpp = 18;

	u32 bpp = 0, data_rate_khz = 0;

	u32 bpp = 0, data_rate_khz = 0, tmds_max_clock = 0;



	if (dp_panel->dsc_en)

		min_supported_bpp = 24;
@@ -2183,6 +2183,7 @@ static u32 dp_panel_get_supported_bpp(struct dp_panel *dp_panel, 


	link_info = &dp_panel->link_info;

	data_rate_khz = link_info->num_lanes * link_info->rate * 8;

	tmds_max_clock = dp_panel->connector->display_info.max_tmds_clock;



	for (; bpp > min_supported_bpp; bpp -= 6) {

		if (dp_panel->dsc_en) {
@@ -2199,6 +2200,10 @@ static u32 dp_panel_get_supported_bpp(struct dp_panel *dp_panel, 
				continue;

		}



		if (tmds_max_clock > 0 &&

		    mult_frac(mode_pclk_khz, bpp, 24)  > tmds_max_clock)

			continue;



		if (mode_pclk_khz * bpp <= data_rate_khz)

			break;

	}