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Commit 1c3275b6 authored by Sudhakar Rajashekhara's avatar Sudhakar Rajashekhara Committed by David Woodhouse
Browse files

mtd: nand: davinci: correct 4-bit error correction 



On TI's DA830/OMAP-L137, DA850/OMAP-L138 and DM365, after setting the
4BITECC_ADD_CALC_START bit in the NAND Flash control register to 1 and
before waiting for the NAND Flash status register to be equal to 1, 2 or
3, we have to wait till the ECC HW goes to correction state.  Without this
wait, ECC correction calculations will not be proper.

This has been tested on DA830/OMAP-L137, DA850/OMAP-L138, DM355 and DM365
EVMs.

Signed-off-by: default avatarSudhakar Rajashekhara <sudhakar.raj@ti.com>
Acked-by: default avatarSneha Narnakaje <nsnehaprabha@ti.com>
Signed-off-by: default avatarAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: default avatarArtem Bityutskiy <Artem.Bityutskiy@nokia.com>
Signed-off-by: default avatarDavid Woodhouse <David.Woodhouse@intel.com>
parent 58373ff0

drivers/mtd/nand/davinci_nand.c

+17 −0
Original line number Diff line number Diff line
@@ -311,7 +311,9 @@ static int nand_davinci_correct_4bit(struct mtd_info *mtd, 
	unsigned short ecc10[8];

	unsigned short *ecc16;

	u32 syndrome[4];

	u32 ecc_state;

	unsigned num_errors, corrected;

	unsigned long timeo = jiffies + msecs_to_jiffies(100);



	/* All bytes 0xff?  It's an erased page; ignore its ECC. */

	for (i = 0; i < 10; i++) {
@@ -361,6 +363,21 @@ static int nand_davinci_correct_4bit(struct mtd_info *mtd, 
	 */

	davinci_nand_writel(info, NANDFCR_OFFSET,

			davinci_nand_readl(info, NANDFCR_OFFSET) | BIT(13));



	/*

	 * ECC_STATE field reads 0x3 (Error correction complete) immediately

	 * after setting the 4BITECC_ADD_CALC_START bit. So if you immediately

	 * begin trying to poll for the state, you may fall right out of your

	 * loop without any of the correction calculations having taken place.

	 * The recommendation from the hardware team is to wait till ECC_STATE

	 * reads less than 4, which means ECC HW has entered correction state.

	 */

	do {

		ecc_state = (davinci_nand_readl(info,

				NANDFSR_OFFSET) >> 8) & 0x0f;

		cpu_relax();

	} while ((ecc_state < 4) && time_before(jiffies, timeo));



	for (;;) {

		u32	fsr = davinci_nand_readl(info, NANDFSR_OFFSET);