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Commit 1c0b7df5 authored by Joakim Tjernlund's avatar Joakim Tjernlund Committed by Li Yang
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soc: fsl: qe: gpio: Add qe_gpio_set_multiple 



This cousin to gpio-mpc8xxx was lacking a multiple pins method,
add one.

Signed-off-by: default avatarJoakim Tjernlund <joakim.tjernlund@infinera.com>
Reviewed-by: default avatarQiang Zhao <qiang.zhao@nxp.com>
Signed-off-by: default avatarLi Yang <leoyang.li@nxp.com>
parent ce397d21

drivers/soc/fsl/qe/gpio.c

+28 −0
Original line number Diff line number Diff line
@@ -83,6 +83,33 @@ static void qe_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val) 
	spin_unlock_irqrestore(&qe_gc->lock, flags);

}



static void qe_gpio_set_multiple(struct gpio_chip *gc,

				 unsigned long *mask, unsigned long *bits)

{

	struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);

	struct qe_gpio_chip *qe_gc = gpiochip_get_data(gc);

	struct qe_pio_regs __iomem *regs = mm_gc->regs;

	unsigned long flags;

	int i;



	spin_lock_irqsave(&qe_gc->lock, flags);



	for (i = 0; i < gc->ngpio; i++) {

		if (*mask == 0)

			break;

		if (__test_and_clear_bit(i, mask)) {

			if (test_bit(i, bits))

				qe_gc->cpdata |= (1U << (QE_PIO_PINS - 1 - i));

			else

				qe_gc->cpdata &= ~(1U << (QE_PIO_PINS - 1 - i));

		}

	}



	out_be32(&regs->cpdata, qe_gc->cpdata);



	spin_unlock_irqrestore(&qe_gc->lock, flags);

}



static int qe_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)

{

	struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
@@ -298,6 +325,7 @@ static int __init qe_add_gpiochips(void) 
		gc->direction_output = qe_gpio_dir_out;

		gc->get = qe_gpio_get;

		gc->set = qe_gpio_set;

		gc->set_multiple = qe_gpio_set_multiple;



		ret = of_mm_gpiochip_add_data(np, mm_gc, qe_gc);

		if (ret)