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Commit 1bf7067c authored by Linus Torvalds's avatar Linus Torvalds
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Merge branch 'locking-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull locking updates from Ingo Molnar:
 "The main changes are:

   - 'qspinlock' support, enabled on x86: queued spinlocks - these are
     now the spinlock variant used by x86 as they outperform ticket
     spinlocks in every category.  (Waiman Long)

   - 'pvqspinlock' support on x86: paravirtualized variant of queued
     spinlocks.  (Waiman Long, Peter Zijlstra)

   - 'qrwlock' support, enabled on x86: queued rwlocks.  Similar to
     queued spinlocks, they are now the variant used by x86:

       CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y
       CONFIG_QUEUED_SPINLOCKS=y
       CONFIG_ARCH_USE_QUEUED_RWLOCKS=y
       CONFIG_QUEUED_RWLOCKS=y

   - various lockdep fixlets

   - various locking primitives cleanups, further WRITE_ONCE()
     propagation"

* 'locking-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (24 commits)
  locking/lockdep: Remove hard coded array size dependency
  locking/qrwlock: Don't contend with readers when setting _QW_WAITING
  lockdep: Do not break user-visible string
  locking/arch: Rename set_mb() to smp_store_mb()
  locking/arch: Add WRITE_ONCE() to set_mb()
  rtmutex: Warn if trylock is called from hard/softirq context
  arch: Remove __ARCH_HAVE_CMPXCHG
  locking/rtmutex: Drop usage of __HAVE_ARCH_CMPXCHG
  locking/qrwlock: Rename QUEUE_RWLOCK to QUEUED_RWLOCKS
  locking/pvqspinlock: Rename QUEUED_SPINLOCK to QUEUED_SPINLOCKS
  locking/pvqspinlock: Replace xchg() by the more descriptive set_mb()
  locking/pvqspinlock, x86: Enable PV qspinlock for Xen
  locking/pvqspinlock, x86: Enable PV qspinlock for KVM
  locking/pvqspinlock, x86: Implement the paravirt qspinlock call patching
  locking/pvqspinlock: Implement simple paravirt support for the qspinlock
  locking/qspinlock: Revert to test-and-set on hypervisors
  locking/qspinlock: Use a simple write to grab the lock
  locking/qspinlock: Optimize for smaller NR_CPUS
  locking/qspinlock: Extract out code snippets for the next patch
  locking/qspinlock: Add pending bit
  ...
parents fc934d40 68722101

Documentation/memory-barriers.txt

+3 −3
Original line number Diff line number Diff line
@@ -1673,7 +1673,7 @@ CPU from reordering them. 


There are some more advanced barrier functions:



 (*) set_mb(var, value)

 (*) smp_store_mb(var, value)



     This assigns the value to the variable and then inserts a full memory

     barrier after it, depending on the function.  It isn't guaranteed to
@@ -1985,7 +1985,7 @@ after it has altered the task state: 
	CPU 1

	===============================

	set_current_state();

	  set_mb();

	  smp_store_mb();

	    STORE current->state

	    <general barrier>

	LOAD event_indicated
@@ -2026,7 +2026,7 @@ between the STORE to indicate the event and the STORE to set TASK_RUNNING: 
	CPU 1				CPU 2

	===============================	===============================

	set_current_state();		STORE event_indicated

	  set_mb();			wake_up();

	  smp_store_mb();		wake_up();

	    STORE current->state	  <write barrier>

	    <general barrier>		  STORE current->state

	LOAD event_indicated

arch/alpha/include/asm/cmpxchg.h

+0 −2
Original line number Diff line number Diff line
@@ -66,6 +66,4 @@ 
#undef __ASM__MB

#undef ____cmpxchg



#define __HAVE_ARCH_CMPXCHG 1



#endif /* _ALPHA_CMPXCHG_H */

arch/arm/include/asm/barrier.h

+1 −1
Original line number Diff line number Diff line
@@ -81,7 +81,7 @@ do { \ 
#define read_barrier_depends()		do { } while(0)

#define smp_read_barrier_depends()	do { } while(0)



#define set_mb(var, value)	do { var = value; smp_mb(); } while (0)

#define smp_store_mb(var, value)	do { WRITE_ONCE(var, value); smp_mb(); } while (0)



#define smp_mb__before_atomic()	smp_mb()

#define smp_mb__after_atomic()	smp_mb()

arch/arm64/include/asm/barrier.h

+1 −1
Original line number Diff line number Diff line
@@ -114,7 +114,7 @@ do { \ 
#define read_barrier_depends()		do { } while(0)

#define smp_read_barrier_depends()	do { } while(0)



#define set_mb(var, value)	do { var = value; smp_mb(); } while (0)

#define smp_store_mb(var, value)	do { WRITE_ONCE(var, value); smp_mb(); } while (0)

#define nop()		asm volatile("nop");



#define smp_mb__before_atomic()	smp_mb()

arch/avr32/include/asm/cmpxchg.h

+0 −2
Original line number Diff line number Diff line
@@ -70,8 +70,6 @@ extern unsigned long __cmpxchg_u64_unsupported_on_32bit_kernels( 
   if something tries to do an invalid cmpxchg().  */

extern void __cmpxchg_called_with_bad_pointer(void);



#define __HAVE_ARCH_CMPXCHG 1



static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old,

				      unsigned long new, int size)

{