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Commit 1bef24ba authored by John Keeping's avatar John Keeping Committed by Sean Paul
Browse files

drm/rockchip: dw-mipi-dsi: fix escape clock rate 



This clock rate is derived from the PHY PLL, so it should be calculated
dynamically.  This calculation is the same as that used by the vendor
kernel and ensures that the escape clock runs at <20MHz as required by
the MIPI specification.

Signed-off-by: default avatarJohn Keeping <john@metanate.com>
Reviewed-by: default avatarChris Zhong <zyw@rock-chips.com>
Reviewed-by: default avatarSean Paul <seanpaul@chromium.org>
Signed-off-by: default avatarSean Paul <seanpaul@chromium.org>
Link: http://patchwork.freedesktop.org/patch/msgid/20170224125506.21533-14-john@metanate.com
parent 96ad6f0b

drivers/gpu/drm/rockchip/dw-mipi-dsi.c

+11 −1
Original line number Diff line number Diff line
@@ -712,11 +712,21 @@ static void dw_mipi_dsi_disable(struct dw_mipi_dsi *dsi) 


static void dw_mipi_dsi_init(struct dw_mipi_dsi *dsi)

{

	/*

	 * The maximum permitted escape clock is 20MHz and it is derived from

	 * lanebyteclk, which is running at "lane_mbps / 8".  Thus we want:

	 *

	 *     (lane_mbps >> 3) / esc_clk_division < 20

	 * which is:

	 *     (lane_mbps >> 3) / 20 > esc_clk_division

	 */

	u32 esc_clk_division = (dsi->lane_mbps >> 3) / 20 + 1;



	dsi_write(dsi, DSI_PWR_UP, RESET);

	dsi_write(dsi, DSI_PHY_RSTZ, PHY_DISFORCEPLL | PHY_DISABLECLK

		  | PHY_RSTZ | PHY_SHUTDOWNZ);

	dsi_write(dsi, DSI_CLKMGR_CFG, TO_CLK_DIVIDSION(10) |

		  TX_ESC_CLK_DIVIDSION(7));

		  TX_ESC_CLK_DIVIDSION(esc_clk_division));

}



static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi,