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Commit 1b59fb03 authored by Evan Quan's avatar Evan Quan Committed by Alex Deucher
Browse files

drm/amdgpu: add MP1 and THM hw ip base reg offset 



Signed-off-by: default avatarEvan Quan <evan.quan@amd.com>
Reviewed-by: default avatarRex Zhu <Rex.Zhu@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 2d4f9020

drivers/gpu/drm/amd/amdgpu/amdgpu.h

+2 −0
Original line number Diff line number Diff line
@@ -1379,6 +1379,7 @@ enum amd_hw_ip_block_type { 
	ATHUB_HWIP,

	NBIO_HWIP,

	MP0_HWIP,

	MP1_HWIP,

	UVD_HWIP,

	VCN_HWIP = UVD_HWIP,

	VCE_HWIP,
@@ -1388,6 +1389,7 @@ enum amd_hw_ip_block_type { 
	SMUIO_HWIP,

	PWR_HWIP,

	NBIF_HWIP,

	THM_HWIP,

	MAX_HWIP

};

drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c

+2 −1
Original line number Diff line number Diff line
@@ -38,6 +38,7 @@ int vega10_reg_base_init(struct amdgpu_device *adev) 
		adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i]));

		adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i]));

		adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i]));

		adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i]));

		adev->reg_offset[UVD_HWIP][i] = (uint32_t *)(&(UVD_BASE.instance[i]));

		adev->reg_offset[VCE_HWIP][i] = (uint32_t *)(&(VCE_BASE.instance[i]));

		adev->reg_offset[VCN_HWIP][i] = (uint32_t *)(&(VCN_BASE.instance[i]));
@@ -49,7 +50,7 @@ int vega10_reg_base_init(struct amdgpu_device *adev) 
		adev->reg_offset[SMUIO_HWIP][i] = (uint32_t *)(&(SMUIO_BASE.instance[i]));

		adev->reg_offset[PWR_HWIP][i] = (uint32_t *)(&(PWR_BASE.instance[i]));

		adev->reg_offset[NBIF_HWIP][i] = (uint32_t *)(&(NBIF_BASE.instance[i]));



		adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i]));

	}

	return 0;

}