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Commit 1b06bd8d authored by David Gilhooley's avatar David Gilhooley Committed by Will Deacon
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arm64: Add MIDR encoding for NVIDIA CPUs 



This patch adds the MIDR encodings for NVIDIA as well as
the Denver and Carmel CPUs used in Tegra SoCs.

Signed-off-by: default avatarDavid Gilhooley <dgilhooley@nvidia.com>
Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
parent 05c58752

arch/arm64/include/asm/cputype.h

+6 −0
Original line number Diff line number Diff line
@@ -75,6 +75,7 @@ 
#define ARM_CPU_IMP_CAVIUM		0x43

#define ARM_CPU_IMP_BRCM		0x42

#define ARM_CPU_IMP_QCOM		0x51

#define ARM_CPU_IMP_NVIDIA		0x4E



#define ARM_CPU_PART_AEM_V8		0xD0F

#define ARM_CPU_PART_FOUNDATION		0xD00
@@ -99,6 +100,9 @@ 
#define QCOM_CPU_PART_FALKOR		0xC00

#define QCOM_CPU_PART_KRYO		0x200



#define NVIDIA_CPU_PART_DENVER		0x003

#define NVIDIA_CPU_PART_CARMEL		0x004



#define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53)

#define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57)

#define MIDR_CORTEX_A72 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A72)
@@ -114,6 +118,8 @@ 
#define MIDR_QCOM_FALKOR_V1 MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_FALKOR_V1)

#define MIDR_QCOM_FALKOR MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_FALKOR)

#define MIDR_QCOM_KRYO MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO)

#define MIDR_NVIDIA_DENVER MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_DENVER)

#define MIDR_NVIDIA_CARMEL MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_CARMEL)



#ifndef __ASSEMBLY__