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Commit 1b02dcb9 authored by Linus Torvalds's avatar Linus Torvalds
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Merge tag 'dmaengine-4.17-rc1' of git://git.infradead.org/users/vkoul/slave-dma

Pull dmaengine updates from Vinod Koul:
 "This time we have couple of new drivers along with updates to drivers:

   - new drivers for the DesignWare AXI DMAC and MediaTek High-Speed DMA
     controllers

   - stm32 dma and qcom bam dma driver updates

   - norandom test option for dmatest"

* tag 'dmaengine-4.17-rc1' of git://git.infradead.org/users/vkoul/slave-dma: (30 commits)
  dmaengine: stm32-dma: properly mask irq bits
  dmaengine: stm32-dma: fix max items per transfer
  dmaengine: stm32-dma: fix DMA IRQ status handling
  dmaengine: stm32-dma: Improve memory burst management
  dmaengine: stm32-dma: fix typo and reported checkpatch warnings
  dmaengine: stm32-dma: fix incomplete configuration in cyclic mode
  dmaengine: stm32-dma: threshold manages with bitfield feature
  dt-bindings: stm32-dma: introduce DMA features bitfield
  dt-bindings: rcar-dmac: Document r8a77470 support
  dmaengine: rcar-dmac: Fix too early/late system suspend/resume callbacks
  dmaengine: dw-axi-dmac: fix spelling mistake: "catched" -> "caught"
  dmaengine: edma: Check the memory allocation for the memcpy dma device
  dmaengine: at_xdmac: fix rare residue corruption
  dmaengine: mediatek: update MAINTAINERS entry with MediaTek DMA driver
  dmaengine: mediatek: Add MediaTek High-Speed DMA controller for MT7622 and MT7623 SoC
  dt-bindings: dmaengine: Add MediaTek High-Speed DMA controller bindings
  dt-bindings: Document the Synopsys DW AXI DMA bindings
  dmaengine: Introduce DW AXI DMAC driver
  dmaengine: pl330: fix a race condition in case of threaded irqs
  dmaengine: imx-sdma: fix pagefault when channel is disabled during interrupt
  ...
parents 92589cbd 2ffb850e
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MediaTek High-Speed DMA Controller
==================================

This device follows the generic DMA bindings defined in dma/dma.txt.

Required properties:

- compatible:	Must be one of
		  "mediatek,mt7622-hsdma": for MT7622 SoC
		  "mediatek,mt7623-hsdma": for MT7623 SoC
- reg:		Should contain the register's base address and length.
- interrupts:	Should contain a reference to the interrupt used by this
		device.
- clocks:	Should be the clock specifiers corresponding to the entry in
		clock-names property.
- clock-names:	Should contain "hsdma" entries.
- power-domains: Phandle to the power domain that the device is part of
- #dma-cells: 	The length of the DMA specifier, must be <1>. This one cell
		in dmas property of a client device represents the channel
		number.
Example:

        hsdma: dma-controller@1b007000 {
		compatible = "mediatek,mt7623-hsdma";
		reg = <0 0x1b007000 0 0x1000>;
		interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&ethsys CLK_ETHSYS_HSDMA>;
		clock-names = "hsdma";
		power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
		#dma-cells = <1>;
	};

DMA clients must use the format described in dma/dma.txt file.
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@@ -15,6 +15,10 @@ Required properties:
  the secure world.
- qcom,controlled-remotely : optional, indicates that the bam is controlled by
  remote proccessor i.e. execution environment.
- num-channels : optional, indicates supported number of DMA channels in a
  remotely controlled bam.
- qcom,num-ees : optional, indicates supported number of Execution Environments
  in a remotely controlled bam.

Example:

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@@ -18,6 +18,7 @@ Required Properties:
	      Examples with soctypes are:
		- "renesas,dmac-r8a7743" (RZ/G1M)
		- "renesas,dmac-r8a7745" (RZ/G1E)
		- "renesas,dmac-r8a77470" (RZ/G1C)
		- "renesas,dmac-r8a7790" (R-Car H2)
		- "renesas,dmac-r8a7791" (R-Car M2-W)
		- "renesas,dmac-r8a7792" (R-Car V2H)
@@ -26,6 +27,7 @@ Required Properties:
		- "renesas,dmac-r8a7795" (R-Car H3)
		- "renesas,dmac-r8a7796" (R-Car M3-W)
		- "renesas,dmac-r8a77970" (R-Car V3M)
		- "renesas,dmac-r8a77980" (R-Car V3H)

- reg: base address and length of the registers block for the DMAC

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@@ -11,6 +11,7 @@ Required Properties:
	  - "renesas,r8a7794-usb-dmac" (R-Car E2)
	  - "renesas,r8a7795-usb-dmac" (R-Car H3)
	  - "renesas,r8a7796-usb-dmac" (R-Car M3-W)
	  - "renesas,r8a77965-usb-dmac" (R-Car M3-N)
- reg: base address and length of the registers block for the DMAC
- interrupts: interrupt specifiers for the DMAC, one for each entry in
  interrupt-names.
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Synopsys DesignWare AXI DMA Controller

Required properties:
- compatible: "snps,axi-dma-1.01a"
- reg: Address range of the DMAC registers. This should include
  all of the per-channel registers.
- interrupt: Should contain the DMAC interrupt number.
- interrupt-parent: Should be the phandle for the interrupt controller
  that services interrupts for this device.
- dma-channels: Number of channels supported by hardware.
- snps,dma-masters: Number of AXI masters supported by the hardware.
- snps,data-width: Maximum AXI data width supported by hardware.
  (0 - 8bits, 1 - 16bits, 2 - 32bits, ..., 6 - 512bits)
- snps,priority: Priority of channel. Array size is equal to the number of
  dma-channels. Priority value must be programmed within [0:dma-channels-1]
  range. (0 - minimum priority)
- snps,block-size: Maximum block size supported by the controller channel.
  Array size is equal to the number of dma-channels.

Optional properties:
- snps,axi-max-burst-len: Restrict master AXI burst length by value specified
  in this property. If this property is missing the maximum AXI burst length
  supported by DMAC is used. [1:256]

Example:

dmac: dma-controller@80000 {
	compatible = "snps,axi-dma-1.01a";
	reg = <0x80000 0x400>;
	clocks = <&core_clk>, <&cfgr_clk>;
	clock-names = "core-clk", "cfgr-clk";
	interrupt-parent = <&intc>;
	interrupts = <27>;

	dma-channels = <4>;
	snps,dma-masters = <2>;
	snps,data-width = <3>;
	snps,block-size = <4096 4096 4096 4096>;
	snps,priority = <0 1 2 3>;
	snps,axi-max-burst-len = <16>;
};
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