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Commit 1b000845 authored by Mahesh Kumar's avatar Mahesh Kumar Committed by Rodrigo Vivi
Browse files

drm/i915/cnl: Fix PORT_TX_DW5/7 register address 



Register Address for CNL_PORT_DW5_LN0_D is 0x162E54, but current code is
defining it as 0x162ED4. Similarly for CNL_PORT_DW7_LN0_D register address
is defined 0x162EDC instead of 0x162E5C, fix it.

Signed-off-by: default avatarMahesh Kumar <mahesh1.kumar@intel.com>
Fixes: 04416108 ("drm/i915/cnl: Add registers related to voltage swing sequences.")
Reviewed-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180215095643.3844-2-mahesh1.kumar@intel.com


(cherry picked from commit e1039626)
Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
parent 72a6d72c

drivers/gpu/drm/i915/i915_reg.h

+2 −2
Original line number Diff line number Diff line
@@ -2027,7 +2027,7 @@ enum i915_power_well_id { 
#define _CNL_PORT_TX_DW5_LN0_AE		0x162454

#define _CNL_PORT_TX_DW5_LN0_B		0x162654

#define _CNL_PORT_TX_DW5_LN0_C		0x162C54

#define _CNL_PORT_TX_DW5_LN0_D		0x162ED4

#define _CNL_PORT_TX_DW5_LN0_D		0x162E54

#define _CNL_PORT_TX_DW5_LN0_F		0x162854

#define CNL_PORT_TX_DW5_GRP(port)	_MMIO_PORT6(port, \

						    _CNL_PORT_TX_DW5_GRP_AE, \
@@ -2058,7 +2058,7 @@ enum i915_power_well_id { 
#define _CNL_PORT_TX_DW7_LN0_AE		0x16245C

#define _CNL_PORT_TX_DW7_LN0_B		0x16265C

#define _CNL_PORT_TX_DW7_LN0_C		0x162C5C

#define _CNL_PORT_TX_DW7_LN0_D		0x162EDC

#define _CNL_PORT_TX_DW7_LN0_D		0x162E5C

#define _CNL_PORT_TX_DW7_LN0_F		0x16285C

#define CNL_PORT_TX_DW7_GRP(port)	_MMIO_PORT6(port, \

						    _CNL_PORT_TX_DW7_GRP_AE, \