Loading arch/arm64/boot/dts/qcom/kona.dtsi +0 −10 Original line number Diff line number Diff line Loading @@ -19,7 +19,6 @@ #include <dt-bindings/soc/qcom,ipcc.h> #include <dt-bindings/soc/qcom,rpmh-rsc.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/soc/qcom,dcc_v2.h> #include "kona-regulators.dtsi" Loading Loading @@ -651,15 +650,6 @@ reg-names = "pshold-base", "tcsr-boot-misc-detect"; }; dcc: dcc_v2@1023000 { compatible = "qcom,dcc-v2"; reg = <0x1023000 0x1000>, <0x103a000 0x6000>; reg-names = "dcc-base", "dcc-ram-base"; dcc-ram-offset = <0x1a000>; }; mdm0: qcom,mdm0 { compatible = "qcom,ext-sdx55m"; cell-index = <0>; Loading Loading
arch/arm64/boot/dts/qcom/kona.dtsi +0 −10 Original line number Diff line number Diff line Loading @@ -19,7 +19,6 @@ #include <dt-bindings/soc/qcom,ipcc.h> #include <dt-bindings/soc/qcom,rpmh-rsc.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/soc/qcom,dcc_v2.h> #include "kona-regulators.dtsi" Loading Loading @@ -651,15 +650,6 @@ reg-names = "pshold-base", "tcsr-boot-misc-detect"; }; dcc: dcc_v2@1023000 { compatible = "qcom,dcc-v2"; reg = <0x1023000 0x1000>, <0x103a000 0x6000>; reg-names = "dcc-base", "dcc-ram-base"; dcc-ram-offset = <0x1a000>; }; mdm0: qcom,mdm0 { compatible = "qcom,ext-sdx55m"; cell-index = <0>; Loading