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Commit 1ad9a576 authored by Jason Cooper's avatar Jason Cooper
Browse files

Merge branch 'irqchip/mvebu' into irqchip/core

parents 7cf03c9f 0407dace

Documentation/devicetree/bindings/interrupt-controller/marvell,odmi-controller.txt

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* Marvell ODMI for MSI support



Some Marvell SoCs have an On-Die Message Interrupt (ODMI) controller

which can be used by on-board peripheral for MSI interrupts.



Required properties:



- compatible           : The value here should contain "marvell,odmi-controller".



- interrupt,controller : Identifies the node as an interrupt controller.



- msi-controller       : Identifies the node as an MSI controller.



- marvell,odmi-frames  : Number of ODMI frames available. Each frame

                         provides a number of events.



- reg                  : List of register definitions, one for each

                         ODMI frame.



- marvell,spi-base     : List of GIC base SPI interrupts, one for each

                         ODMI frame. Those SPI interrupts are 0-based,

                         i.e marvell,spi-base = <128> will use SPI #96.

                         See Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt

                         for details about the GIC Device Tree binding.



- interrupt-parent     : Reference to the parent interrupt controller.



Example:



	odmi: odmi@300000 {

		compatible = "marvell,odmi-controller";

		interrupt-controller;

		msi-controller;

		marvell,odmi-frames = <4>;

		reg = <0x300000 0x4000>,

		      <0x304000 0x4000>,

		      <0x308000 0x4000>,

		      <0x30C000 0x4000>;

		marvell,spi-base = <128>, <136>, <144>, <152>;

	};

drivers/irqchip/Kconfig

+4 −0
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@@ -229,3 +229,7 @@ config IRQ_MXS 
	def_bool y if MACH_ASM9260 || ARCH_MXS

	select IRQ_DOMAIN

	select STMP_DEVICE



config MVEBU_ODMI

	bool

	select GENERIC_MSI_IRQ_DOMAIN

drivers/irqchip/Makefile

+1 −0
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@@ -62,3 +62,4 @@ obj-$(CONFIG_ARCH_SA1100) += irq-sa11x0.o 
obj-$(CONFIG_INGENIC_IRQ)		+= irq-ingenic.o

obj-$(CONFIG_IMX_GPCV2)			+= irq-imx-gpcv2.o

obj-$(CONFIG_PIC32_EVIC)		+= irq-pic32-evic.o

obj-$(CONFIG_MVEBU_ODMI)		+= irq-mvebu-odmi.o

drivers/irqchip/irq-gic-v2m.c

+1 −13
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@@ -92,18 +92,6 @@ static struct msi_domain_info gicv2m_msi_domain_info = { 
	.chip	= &gicv2m_msi_irq_chip,

};



static int gicv2m_set_affinity(struct irq_data *irq_data,

			       const struct cpumask *mask, bool force)

{

	int ret;



	ret = irq_chip_set_affinity_parent(irq_data, mask, force);

	if (ret == IRQ_SET_MASK_OK)

		ret = IRQ_SET_MASK_OK_DONE;



	return ret;

}



static void gicv2m_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)

{

	struct v2m_data *v2m = irq_data_get_irq_chip_data(data);
@@ -122,7 +110,7 @@ static struct irq_chip gicv2m_irq_chip = { 
	.irq_mask		= irq_chip_mask_parent,

	.irq_unmask		= irq_chip_unmask_parent,

	.irq_eoi		= irq_chip_eoi_parent,

	.irq_set_affinity	= gicv2m_set_affinity,

	.irq_set_affinity	= irq_chip_set_affinity_parent,

	.irq_compose_msi_msg	= gicv2m_compose_msi_msg,

};

drivers/irqchip/irq-gic.c

+1 −1
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@@ -319,7 +319,7 @@ static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val, 
	writel_relaxed(val | bit, reg);

	raw_spin_unlock_irqrestore(&irq_controller_lock, flags);



	return IRQ_SET_MASK_OK;

	return IRQ_SET_MASK_OK_DONE;

}

#endif