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Commit 1a8359e4 authored by Alan Cox's avatar Alan Cox Committed by Ingo Molnar
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x86/mid: Remove Intel Moorestown 



All production devices operate in the Oaktrail configuration
with legacy PC elements present and an ACPI BIOS. Continue
stripping out the Moorestown elements from the tree leaving
Medfield.

Signed-off-by: default avatarAlan Cox <alan@linux.intel.com>
Cc: jacob.jun.pan@linux.intel.com
Link: http://lkml.kernel.org/n/tip-fvm1hgpq99jln6l0fbek68ik@git.kernel.org


Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
parent d450c088

arch/x86/Kconfig

+0 −21
Original line number Original line Diff line number Diff line
@@ -418,27 +418,6 @@ if X86_WANT_INTEL_MID 
config X86_INTEL_MID

config X86_INTEL_MID

	bool

	bool





config X86_MRST

       bool "Moorestown MID platform"

	depends on PCI

	depends on PCI_GOANY

	depends on X86_IO_APIC

	select X86_INTEL_MID

	select SFI

	select DW_APB_TIMER

	select APB_TIMER

	select I2C

	select SPI

	select INTEL_SCU_IPC

	select X86_PLATFORM_DEVICES

	---help---

	  Moorestown is Intel's Low Power Intel Architecture (LPIA) based Moblin

	  Internet Device(MID) platform. Moorestown consists of two chips:

	  Lincroft (CPU core, graphics, and memory controller) and Langwell IOH.

	  Unlike standard x86 PCs, Moorestown does not have many legacy devices

	  nor standard legacy replacement devices/features. e.g. Moorestown does

	  not contain i8259, i8254, HPET, legacy BIOS, most of the io ports.



config X86_MDFLD

config X86_MDFLD

       bool "Medfield MID platform"

       bool "Medfield MID platform"

	depends on PCI

	depends on PCI

arch/x86/include/asm/mrst.h

+2 −2
Original line number Original line Diff line number Diff line
@@ -26,8 +26,8 @@ extern struct sfi_rtc_table_entry sfi_mrtc_array[]; 
 * identified via MSRs.

 * identified via MSRs.

 */

 */

enum mrst_cpu_type {

enum mrst_cpu_type {

	MRST_CPU_CHIP_LINCROFT = 1,

	/* 1 was Moorestown */

	MRST_CPU_CHIP_PENWELL,

	MRST_CPU_CHIP_PENWELL = 2,

};

};





extern enum mrst_cpu_type __mrst_cpu_chip;

extern enum mrst_cpu_type __mrst_cpu_chip;

arch/x86/platform/mrst/Makefile

+0 −1
Original line number Original line Diff line number Diff line 
obj-$(CONFIG_X86_INTEL_MID)	+= mrst.o

obj-$(CONFIG_X86_INTEL_MID)	+= mrst.o

obj-$(CONFIG_X86_INTEL_MID)	+= vrtc.o

obj-$(CONFIG_X86_INTEL_MID)	+= vrtc.o

obj-$(CONFIG_EARLY_PRINTK_INTEL_MID)	+= early_printk_mrst.o
 
obj-$(CONFIG_EARLY_PRINTK_INTEL_MID)	+= early_printk_mrst.o
 
obj-$(CONFIG_X86_MRST)		+= pmu.o

arch/x86/platform/mrst/mrst.c

+24 −40
Original line number Original line Diff line number Diff line
@@ -78,15 +78,10 @@ int sfi_mrtc_num; 




static void mrst_power_off(void)

static void mrst_power_off(void)

{

{

	if (__mrst_cpu_chip == MRST_CPU_CHIP_LINCROFT)

		intel_scu_ipc_simple_command(IPCMSG_COLD_RESET, 1);

}

}





static void mrst_reboot(void)

static void mrst_reboot(void)

{

{

	if (__mrst_cpu_chip == MRST_CPU_CHIP_LINCROFT)

		intel_scu_ipc_simple_command(IPCMSG_COLD_RESET, 0);

	else

	intel_scu_ipc_simple_command(IPCMSG_COLD_BOOT, 0);

	intel_scu_ipc_simple_command(IPCMSG_COLD_BOOT, 0);

}

}
@@ -200,8 +195,7 @@ int __init sfi_parse_mrtc(struct sfi_table_header *table) 




static unsigned long __init mrst_calibrate_tsc(void)

static unsigned long __init mrst_calibrate_tsc(void)

{

{

	unsigned long flags, fast_calibrate;

	unsigned long fast_calibrate;

	if (__mrst_cpu_chip == MRST_CPU_CHIP_PENWELL) {

	u32 lo, hi, ratio, fsb;

	u32 lo, hi, ratio, fsb;





	rdmsr(MSR_IA32_PERF_STATUS, lo, hi);

	rdmsr(MSR_IA32_PERF_STATUS, lo, hi);
@@ -223,11 +217,6 @@ static unsigned long __init mrst_calibrate_tsc(void) 
	lapic_timer_frequency = fsb * 1000 / HZ;

	lapic_timer_frequency = fsb * 1000 / HZ;

	/* mark tsc clocksource as reliable */

	/* mark tsc clocksource as reliable */

	set_cpu_cap(&boot_cpu_data, X86_FEATURE_TSC_RELIABLE);

	set_cpu_cap(&boot_cpu_data, X86_FEATURE_TSC_RELIABLE);

	} else {

		local_irq_save(flags);

		fast_calibrate = apbt_quick_calibrate();

		local_irq_restore(flags);

	}

	

	

	if (fast_calibrate)

	if (fast_calibrate)

		return fast_calibrate;

		return fast_calibrate;
@@ -261,16 +250,11 @@ static void __cpuinit mrst_arch_setup(void) 
{

{

	if (boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model == 0x27)

	if (boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model == 0x27)

		__mrst_cpu_chip = MRST_CPU_CHIP_PENWELL;

		__mrst_cpu_chip = MRST_CPU_CHIP_PENWELL;

	else if (boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model == 0x26)

		__mrst_cpu_chip = MRST_CPU_CHIP_LINCROFT;

	else {

	else {

		pr_err("Unknown Moorestown CPU (%d:%d), default to Lincroft\n",

		pr_err("Unknown Intel MID CPU (%d:%d), default to Penwell\n",

			boot_cpu_data.x86, boot_cpu_data.x86_model);

			boot_cpu_data.x86, boot_cpu_data.x86_model);

		__mrst_cpu_chip = MRST_CPU_CHIP_LINCROFT;

		__mrst_cpu_chip = MRST_CPU_CHIP_PENWELL;

	}

	}

	pr_debug("Moorestown CPU %s identified\n",

		(__mrst_cpu_chip == MRST_CPU_CHIP_LINCROFT) ?

		"Lincroft" : "Penwell");

}

}





/* MID systems don't have i8042 controller */

/* MID systems don't have i8042 controller */

arch/x86/platform/mrst/pmu.c

deleted100644 → 0
+0 −817

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