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Commit 1a7da877 authored by Peter De Schrijver's avatar Peter De Schrijver Committed by Stephen Boyd
Browse files

clk: tegra: fix SS control on PLL enable/disable 



PLL SS was only controlled when setting the PLL rate, not when the PLL itself
is enabled or disabled.

Signed-off-by: default avatarPeter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-by: default avatarJon Mayo <jmayo@nvidia.com>
Tested-by: default avatarThierry Reding <treding@nvidia.com>
Acked-by: default avatarThierry Reding <treding@nvidia.com>
Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
parent de224554

drivers/clk/tegra/clk-pll.c

+24 −20
Original line number Diff line number Diff line
@@ -418,6 +418,26 @@ static void _clk_pll_disable(struct clk_hw *hw) 
	}

}



static void pll_clk_start_ss(struct tegra_clk_pll *pll)

{

	if (pll->params->defaults_set && pll->params->ssc_ctrl_reg) {

		u32 val = pll_readl(pll->params->ssc_ctrl_reg, pll);



		val |= pll->params->ssc_ctrl_en_mask;

		pll_writel(val, pll->params->ssc_ctrl_reg, pll);

	}

}



static void pll_clk_stop_ss(struct tegra_clk_pll *pll)

{

	if (pll->params->defaults_set && pll->params->ssc_ctrl_reg) {

		u32 val = pll_readl(pll->params->ssc_ctrl_reg, pll);



		val &= ~pll->params->ssc_ctrl_en_mask;

		pll_writel(val, pll->params->ssc_ctrl_reg, pll);

	}

}



static int clk_pll_enable(struct clk_hw *hw)

{

	struct tegra_clk_pll *pll = to_clk_pll(hw);
@@ -431,6 +451,8 @@ static int clk_pll_enable(struct clk_hw *hw) 


	ret = clk_pll_wait_for_lock(pll);



	pll_clk_start_ss(pll);



	if (pll->lock)

		spin_unlock_irqrestore(pll->lock, flags);
@@ -445,6 +467,8 @@ static void clk_pll_disable(struct clk_hw *hw) 
	if (pll->lock)

		spin_lock_irqsave(pll->lock, flags);



	pll_clk_stop_ss(pll);



	_clk_pll_disable(hw);



	if (pll->lock)
@@ -716,26 +740,6 @@ static void _update_pll_cpcon(struct tegra_clk_pll *pll, 
	pll_writel_misc(val, pll);

}



static void pll_clk_start_ss(struct tegra_clk_pll *pll)

{

	if (pll->params->defaults_set && pll->params->ssc_ctrl_reg) {

		u32 val = pll_readl(pll->params->ssc_ctrl_reg, pll);



		val |= pll->params->ssc_ctrl_en_mask;

		pll_writel(val, pll->params->ssc_ctrl_reg, pll);

	}

}



static void pll_clk_stop_ss(struct tegra_clk_pll *pll)

{

	if (pll->params->defaults_set && pll->params->ssc_ctrl_reg) {

		u32 val = pll_readl(pll->params->ssc_ctrl_reg, pll);



		val &= ~pll->params->ssc_ctrl_en_mask;

		pll_writel(val, pll->params->ssc_ctrl_reg, pll);

	}

}



static int _program_pll(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,

			unsigned long rate)

{