Loading .mailmap +4 −0 Original line number Diff line number Diff line Loading @@ -48,6 +48,9 @@ Felix Kuhling <fxkuehl@gmx.de> Felix Moeller <felix@derklecks.de> Filipe Lautert <filipe@icewall.org> Franck Bui-Huu <vagabon.xyz@gmail.com> Frank Rowand <frowand.list@gmail.com> <frowand@mvista.com> Frank Rowand <frowand.list@gmail.com> <frank.rowand@am.sony.com> Frank Rowand <frowand.list@gmail.com> <frank.rowand@sonymobile.com> Frank Zago <fzago@systemfabricworks.com> Greg Kroah-Hartman <greg@echidna.(none)> Greg Kroah-Hartman <gregkh@suse.de> Loading Loading @@ -79,6 +82,7 @@ Kay Sievers <kay.sievers@vrfy.org> Kenneth W Chen <kenneth.w.chen@intel.com> Konstantin Khlebnikov <koct9i@gmail.com> <k.khlebnikov@samsung.com> Koushik <raghavendra.koushik@neterion.com> Krzysztof Kozlowski <krzk@kernel.org> <k.kozlowski.k@gmail.com> Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Leonid I Ananiev <leonid.i.ananiev@intel.com> Linas Vepstas <linas@austin.ibm.com> Loading Documentation/devicetree/bindings/arm/cpus.txt +0 −1 Original line number Diff line number Diff line Loading @@ -192,7 +192,6 @@ nodes to be present and contain the properties described below. can be one of: "allwinner,sun6i-a31" "allwinner,sun8i-a23" "arm,psci" "arm,realview-smp" "brcm,bcm-nsp-smp" "brcm,brahma-b15" Loading Documentation/devicetree/bindings/i2c/i2c-rk3x.txt +2 −2 Original line number Diff line number Diff line Loading @@ -6,8 +6,8 @@ RK3xxx SoCs. Required properties : - reg : Offset and length of the register set for the device - compatible : should be "rockchip,rk3066-i2c", "rockchip,rk3188-i2c" or "rockchip,rk3288-i2c". - compatible : should be "rockchip,rk3066-i2c", "rockchip,rk3188-i2c", "rockchip,rk3228-i2c" or "rockchip,rk3288-i2c". - interrupts : interrupt number - clocks : parent clock Loading Documentation/devicetree/bindings/net/mediatek-net.txt +5 −2 Original line number Diff line number Diff line Loading @@ -9,7 +9,8 @@ have dual GMAC each represented by a child node.. Required properties: - compatible: Should be "mediatek,mt7623-eth" - reg: Address and length of the register set for the device - interrupts: Should contain the frame engines interrupt - interrupts: Should contain the three frame engines interrupts in numeric order. These are fe_int0, fe_int1 and fe_int2. - clocks: the clock used by the core - clock-names: the names of the clock listed in the clocks property. These are "ethif", "esw", "gp2", "gp1" Loading Loading @@ -42,7 +43,9 @@ eth: ethernet@1b100000 { <ðsys CLK_ETHSYS_GP2>, <ðsys CLK_ETHSYS_GP1>; clock-names = "ethif", "esw", "gp2", "gp1"; interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW>; interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW GIC_SPI 199 IRQ_TYPE_LEVEL_LOW GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>; power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>; resets = <ðsys MT2701_ETHSYS_ETH_RST>; reset-names = "eth"; Loading Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt +11 −7 Original line number Diff line number Diff line Loading @@ -8,15 +8,19 @@ Required properties: of memory mapped region. - clock-names: from common clock binding: Required elements: "24m" - rockchip,grf: phandle to the syscon managing the "general register files" - #phy-cells : from the generic PHY bindings, must be 0; Example: grf: syscon@ff770000 { compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd"; ... edp_phy: edp-phy { compatible = "rockchip,rk3288-dp-phy"; rockchip,grf = <&grf>; clocks = <&cru SCLK_EDP_24M>; clock-names = "24m"; #phy-cells = <0>; }; }; Loading
.mailmap +4 −0 Original line number Diff line number Diff line Loading @@ -48,6 +48,9 @@ Felix Kuhling <fxkuehl@gmx.de> Felix Moeller <felix@derklecks.de> Filipe Lautert <filipe@icewall.org> Franck Bui-Huu <vagabon.xyz@gmail.com> Frank Rowand <frowand.list@gmail.com> <frowand@mvista.com> Frank Rowand <frowand.list@gmail.com> <frank.rowand@am.sony.com> Frank Rowand <frowand.list@gmail.com> <frank.rowand@sonymobile.com> Frank Zago <fzago@systemfabricworks.com> Greg Kroah-Hartman <greg@echidna.(none)> Greg Kroah-Hartman <gregkh@suse.de> Loading Loading @@ -79,6 +82,7 @@ Kay Sievers <kay.sievers@vrfy.org> Kenneth W Chen <kenneth.w.chen@intel.com> Konstantin Khlebnikov <koct9i@gmail.com> <k.khlebnikov@samsung.com> Koushik <raghavendra.koushik@neterion.com> Krzysztof Kozlowski <krzk@kernel.org> <k.kozlowski.k@gmail.com> Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Leonid I Ananiev <leonid.i.ananiev@intel.com> Linas Vepstas <linas@austin.ibm.com> Loading
Documentation/devicetree/bindings/arm/cpus.txt +0 −1 Original line number Diff line number Diff line Loading @@ -192,7 +192,6 @@ nodes to be present and contain the properties described below. can be one of: "allwinner,sun6i-a31" "allwinner,sun8i-a23" "arm,psci" "arm,realview-smp" "brcm,bcm-nsp-smp" "brcm,brahma-b15" Loading
Documentation/devicetree/bindings/i2c/i2c-rk3x.txt +2 −2 Original line number Diff line number Diff line Loading @@ -6,8 +6,8 @@ RK3xxx SoCs. Required properties : - reg : Offset and length of the register set for the device - compatible : should be "rockchip,rk3066-i2c", "rockchip,rk3188-i2c" or "rockchip,rk3288-i2c". - compatible : should be "rockchip,rk3066-i2c", "rockchip,rk3188-i2c", "rockchip,rk3228-i2c" or "rockchip,rk3288-i2c". - interrupts : interrupt number - clocks : parent clock Loading
Documentation/devicetree/bindings/net/mediatek-net.txt +5 −2 Original line number Diff line number Diff line Loading @@ -9,7 +9,8 @@ have dual GMAC each represented by a child node.. Required properties: - compatible: Should be "mediatek,mt7623-eth" - reg: Address and length of the register set for the device - interrupts: Should contain the frame engines interrupt - interrupts: Should contain the three frame engines interrupts in numeric order. These are fe_int0, fe_int1 and fe_int2. - clocks: the clock used by the core - clock-names: the names of the clock listed in the clocks property. These are "ethif", "esw", "gp2", "gp1" Loading Loading @@ -42,7 +43,9 @@ eth: ethernet@1b100000 { <ðsys CLK_ETHSYS_GP2>, <ðsys CLK_ETHSYS_GP1>; clock-names = "ethif", "esw", "gp2", "gp1"; interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW>; interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW GIC_SPI 199 IRQ_TYPE_LEVEL_LOW GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>; power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>; resets = <ðsys MT2701_ETHSYS_ETH_RST>; reset-names = "eth"; Loading
Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt +11 −7 Original line number Diff line number Diff line Loading @@ -8,15 +8,19 @@ Required properties: of memory mapped region. - clock-names: from common clock binding: Required elements: "24m" - rockchip,grf: phandle to the syscon managing the "general register files" - #phy-cells : from the generic PHY bindings, must be 0; Example: grf: syscon@ff770000 { compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd"; ... edp_phy: edp-phy { compatible = "rockchip,rk3288-dp-phy"; rockchip,grf = <&grf>; clocks = <&cru SCLK_EDP_24M>; clock-names = "24m"; #phy-cells = <0>; }; };