Loading Documentation/devicetree/bindings/display/msm/sde-dp.txt +3 −0 Original line number Diff line number Diff line Loading @@ -100,11 +100,14 @@ Optional properties: - compatible: Must be "qcom,msm-ext-disp" - qcom,dp-low-power-hw-hpd: Low power hardware HPD feature enable control node - qcom,phy-version: Phy version - qcom,pn-swap-lane-map: P/N swap configuration of each lane - pinctrl-names: List of names to assign mdss pin states defined in pinctrl device node Refer to pinctrl-bindings.txt - pinctrl-<0..n>: Lists phandles each pointing to the pin configuration node within a pin controller. These pin configurations are installed in the pinctrl device node. Refer to pinctrl-bindings.txt - qcom,max-lclk-frequency-khz: An integer specifying the max. link clock in KHz supported by Display Port. - qcom,mst-fixed-topology-ports: u32 values of which MST output port to reserve, start from one [Optional child nodes]: These nodes are for devices which are dependent on msm_ext_disp. If msm_ext_disp is disabled then Loading drivers/gpu/drm/drm_dp_mst_topology.c +49 −18 Original line number Diff line number Diff line Loading @@ -51,10 +51,6 @@ static int drm_dp_dpcd_write_payload(struct drm_dp_mst_topology_mgr *mgr, int id, struct drm_dp_payload *payload); static int drm_dp_send_dpcd_write(struct drm_dp_mst_topology_mgr *mgr, struct drm_dp_mst_port *port, int offset, int size, u8 *bytes); static void drm_dp_send_link_address(struct drm_dp_mst_topology_mgr *mgr, struct drm_dp_mst_branch *mstb); static int drm_dp_send_enum_path_resources(struct drm_dp_mst_topology_mgr *mgr, Loading Loading @@ -439,6 +435,7 @@ static bool drm_dp_sideband_parse_remote_dpcd_read(struct drm_dp_sideband_msg_rx if (idx > raw->curlen) goto fail_len; repmsg->u.remote_dpcd_read_ack.num_bytes = raw->msg[idx]; idx++; if (idx > raw->curlen) goto fail_len; Loading Loading @@ -1402,7 +1399,6 @@ static bool drm_dp_validate_guid(struct drm_dp_mst_topology_mgr *mgr, return false; } #if 0 static int build_dpcd_read(struct drm_dp_sideband_msg_tx *msg, u8 port_num, u32 offset, u8 num_bytes) { struct drm_dp_sideband_msg_req_body req; Loading @@ -1415,7 +1411,6 @@ static int build_dpcd_read(struct drm_dp_sideband_msg_tx *msg, u8 port_num, u32 return 0; } #endif static int drm_dp_send_sideband_msg(struct drm_dp_mst_topology_mgr *mgr, bool up, u8 *msg, int len) Loading Loading @@ -1981,28 +1976,63 @@ int drm_dp_update_payload_part2(struct drm_dp_mst_topology_mgr *mgr) } EXPORT_SYMBOL(drm_dp_update_payload_part2); #if 0 /* unused as of yet */ static int drm_dp_send_dpcd_read(struct drm_dp_mst_topology_mgr *mgr, int drm_dp_send_dpcd_read(struct drm_dp_mst_topology_mgr *mgr, struct drm_dp_mst_port *port, int offset, int size) int offset, int size, u8 *bytes) { int len; int ret; struct drm_dp_sideband_msg_tx *txmsg; struct drm_dp_mst_branch *mstb; memset(bytes, 0, size); mstb = drm_dp_get_validated_mstb_ref(mgr, port->parent); if (!mstb) return -EINVAL; txmsg = kzalloc(sizeof(*txmsg), GFP_KERNEL); if (!txmsg) return -ENOMEM; if (!txmsg) { ret = -ENOMEM; goto fail_put; } len = build_dpcd_read(txmsg, port->port_num, 0, 8); txmsg->dst = port->parent; len = build_dpcd_read(txmsg, port->port_num, offset, size); txmsg->dst = mstb; drm_dp_queue_down_tx(mgr, txmsg); ret = drm_dp_mst_wait_tx_reply(mstb, txmsg); if (ret <= 0) { DRM_ERROR("dpcd read failed\n"); goto fail_free_msg; } return 0; if (txmsg->reply.reply_type == 1) { DRM_ERROR("dpcd read nack received\n"); ret = -EINVAL; goto fail_free_msg; } if (port->port_num != txmsg->reply.u.remote_dpcd_read_ack.port_number) { DRM_ERROR("got incorrect port in response\n"); ret = -EINVAL; goto fail_free_msg; } if (size > txmsg->reply.u.remote_dpcd_read_ack.num_bytes) size = txmsg->reply.u.remote_dpcd_read_ack.num_bytes; memcpy(bytes, txmsg->reply.u.remote_dpcd_read_ack.bytes, size); fail_free_msg: kfree(txmsg); fail_put: drm_dp_put_mst_branch_device(mstb); return ret; } #endif EXPORT_SYMBOL(drm_dp_send_dpcd_read); static int drm_dp_send_dpcd_write(struct drm_dp_mst_topology_mgr *mgr, int drm_dp_send_dpcd_write(struct drm_dp_mst_topology_mgr *mgr, struct drm_dp_mst_port *port, int offset, int size, u8 *bytes) { Loading Loading @@ -2038,6 +2068,7 @@ static int drm_dp_send_dpcd_write(struct drm_dp_mst_topology_mgr *mgr, drm_dp_put_mst_branch_device(mstb); return ret; } EXPORT_SYMBOL(drm_dp_send_dpcd_write); static int drm_dp_encode_up_ack_reply(struct drm_dp_sideband_msg_tx *msg, u8 req_type) { Loading drivers/gpu/drm/msm/dp/dp_catalog.c +25 −0 Original line number Diff line number Diff line Loading @@ -882,6 +882,30 @@ static void dp_catalog_ctrl_lane_mapping(struct dp_catalog_ctrl *ctrl, 0xe4); } static void dp_catalog_ctrl_lane_pnswap(struct dp_catalog_ctrl *ctrl, u8 ln_pnswap) { struct dp_catalog_private *catalog; struct dp_io_data *io_data; u32 cfg0, cfg1; catalog = dp_catalog_get_priv(ctrl); cfg0 = 0x0a; cfg1 = 0x0a; cfg0 |= ((ln_pnswap >> 0) & 0x1) << 0; cfg0 |= ((ln_pnswap >> 1) & 0x1) << 2; cfg1 |= ((ln_pnswap >> 2) & 0x1) << 0; cfg1 |= ((ln_pnswap >> 3) & 0x1) << 2; io_data = catalog->io.dp_ln_tx0; dp_write(catalog->exe_mode, io_data, TXn_TX_POL_INV, cfg0); io_data = catalog->io.dp_ln_tx1; dp_write(catalog->exe_mode, io_data, TXn_TX_POL_INV, cfg1); } static void dp_catalog_ctrl_mainlink_ctrl(struct dp_catalog_ctrl *ctrl, bool enable) { Loading Loading @@ -2509,6 +2533,7 @@ struct dp_catalog *dp_catalog_get(struct device *dev, struct dp_parser *parser) .state_ctrl = dp_catalog_ctrl_state_ctrl, .config_ctrl = dp_catalog_ctrl_config_ctrl, .lane_mapping = dp_catalog_ctrl_lane_mapping, .lane_pnswap = dp_catalog_ctrl_lane_pnswap, .mainlink_ctrl = dp_catalog_ctrl_mainlink_ctrl, .set_pattern = dp_catalog_ctrl_set_pattern, .reset = dp_catalog_ctrl_reset, Loading drivers/gpu/drm/msm/dp/dp_catalog.h +14 −0 Original line number Diff line number Diff line /* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. <<<<<<< HEAD ======= * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and * only version 2 as published by the Free Software Foundation. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * >>>>>>> aacf58a... drm/msm/dp: Add P/N swap support for dp phy */ #ifndef _DP_CATALOG_H_ Loading Loading @@ -93,6 +106,7 @@ struct dp_catalog_ctrl { void (*config_ctrl)(struct dp_catalog_ctrl *ctrl, u8 ln_cnt); void (*lane_mapping)(struct dp_catalog_ctrl *ctrl, bool flipped, char *lane_map); void (*lane_pnswap)(struct dp_catalog_ctrl *ctrl, u8 ln_pnswap); void (*mainlink_ctrl)(struct dp_catalog_ctrl *ctrl, bool enable); void (*set_pattern)(struct dp_catalog_ctrl *ctrl, u32 pattern); void (*reset)(struct dp_catalog_ctrl *ctrl); Loading drivers/gpu/drm/msm/dp/dp_catalog_v420.c +25 −0 Original line number Diff line number Diff line Loading @@ -266,6 +266,30 @@ static void dp_catalog_ctrl_update_vx_px_v420(struct dp_catalog_ctrl *ctrl, } } static void dp_catalog_ctrl_lane_pnswap_v420(struct dp_catalog_ctrl *ctrl, u8 ln_pnswap) { struct dp_catalog_private_v420 *catalog; struct dp_io_data *io_data; u32 cfg0, cfg1; catalog = dp_catalog_get_priv_v420(ctrl); cfg0 = 0x0a; cfg1 = 0x0a; cfg0 |= ((ln_pnswap >> 0) & 0x1) << 0; cfg0 |= ((ln_pnswap >> 1) & 0x1) << 2; cfg1 |= ((ln_pnswap >> 2) & 0x1) << 0; cfg1 |= ((ln_pnswap >> 3) & 0x1) << 2; io_data = catalog->io->dp_ln_tx0; dp_write(catalog->exe_mode, io_data, TXn_TX_POL_INV_V420, cfg0); io_data = catalog->io->dp_ln_tx1; dp_write(catalog->exe_mode, io_data, TXn_TX_POL_INV_V420, cfg1); } static void dp_catalog_put_v420(struct dp_catalog *catalog) { struct dp_catalog_private_v420 *catalog_priv; Loading Loading @@ -316,6 +340,7 @@ int dp_catalog_get_v420(struct device *dev, struct dp_catalog *catalog, catalog->panel.config_msa = dp_catalog_panel_config_msa_v420; catalog->ctrl.phy_lane_cfg = dp_catalog_ctrl_phy_lane_cfg_v420; catalog->ctrl.update_vx_px = dp_catalog_ctrl_update_vx_px_v420; catalog->ctrl.lane_pnswap = dp_catalog_ctrl_lane_pnswap_v420; /* Set the default execution mode to hardware mode */ dp_catalog_set_exe_mode_v420(catalog, "hw"); Loading Loading
Documentation/devicetree/bindings/display/msm/sde-dp.txt +3 −0 Original line number Diff line number Diff line Loading @@ -100,11 +100,14 @@ Optional properties: - compatible: Must be "qcom,msm-ext-disp" - qcom,dp-low-power-hw-hpd: Low power hardware HPD feature enable control node - qcom,phy-version: Phy version - qcom,pn-swap-lane-map: P/N swap configuration of each lane - pinctrl-names: List of names to assign mdss pin states defined in pinctrl device node Refer to pinctrl-bindings.txt - pinctrl-<0..n>: Lists phandles each pointing to the pin configuration node within a pin controller. These pin configurations are installed in the pinctrl device node. Refer to pinctrl-bindings.txt - qcom,max-lclk-frequency-khz: An integer specifying the max. link clock in KHz supported by Display Port. - qcom,mst-fixed-topology-ports: u32 values of which MST output port to reserve, start from one [Optional child nodes]: These nodes are for devices which are dependent on msm_ext_disp. If msm_ext_disp is disabled then Loading
drivers/gpu/drm/drm_dp_mst_topology.c +49 −18 Original line number Diff line number Diff line Loading @@ -51,10 +51,6 @@ static int drm_dp_dpcd_write_payload(struct drm_dp_mst_topology_mgr *mgr, int id, struct drm_dp_payload *payload); static int drm_dp_send_dpcd_write(struct drm_dp_mst_topology_mgr *mgr, struct drm_dp_mst_port *port, int offset, int size, u8 *bytes); static void drm_dp_send_link_address(struct drm_dp_mst_topology_mgr *mgr, struct drm_dp_mst_branch *mstb); static int drm_dp_send_enum_path_resources(struct drm_dp_mst_topology_mgr *mgr, Loading Loading @@ -439,6 +435,7 @@ static bool drm_dp_sideband_parse_remote_dpcd_read(struct drm_dp_sideband_msg_rx if (idx > raw->curlen) goto fail_len; repmsg->u.remote_dpcd_read_ack.num_bytes = raw->msg[idx]; idx++; if (idx > raw->curlen) goto fail_len; Loading Loading @@ -1402,7 +1399,6 @@ static bool drm_dp_validate_guid(struct drm_dp_mst_topology_mgr *mgr, return false; } #if 0 static int build_dpcd_read(struct drm_dp_sideband_msg_tx *msg, u8 port_num, u32 offset, u8 num_bytes) { struct drm_dp_sideband_msg_req_body req; Loading @@ -1415,7 +1411,6 @@ static int build_dpcd_read(struct drm_dp_sideband_msg_tx *msg, u8 port_num, u32 return 0; } #endif static int drm_dp_send_sideband_msg(struct drm_dp_mst_topology_mgr *mgr, bool up, u8 *msg, int len) Loading Loading @@ -1981,28 +1976,63 @@ int drm_dp_update_payload_part2(struct drm_dp_mst_topology_mgr *mgr) } EXPORT_SYMBOL(drm_dp_update_payload_part2); #if 0 /* unused as of yet */ static int drm_dp_send_dpcd_read(struct drm_dp_mst_topology_mgr *mgr, int drm_dp_send_dpcd_read(struct drm_dp_mst_topology_mgr *mgr, struct drm_dp_mst_port *port, int offset, int size) int offset, int size, u8 *bytes) { int len; int ret; struct drm_dp_sideband_msg_tx *txmsg; struct drm_dp_mst_branch *mstb; memset(bytes, 0, size); mstb = drm_dp_get_validated_mstb_ref(mgr, port->parent); if (!mstb) return -EINVAL; txmsg = kzalloc(sizeof(*txmsg), GFP_KERNEL); if (!txmsg) return -ENOMEM; if (!txmsg) { ret = -ENOMEM; goto fail_put; } len = build_dpcd_read(txmsg, port->port_num, 0, 8); txmsg->dst = port->parent; len = build_dpcd_read(txmsg, port->port_num, offset, size); txmsg->dst = mstb; drm_dp_queue_down_tx(mgr, txmsg); ret = drm_dp_mst_wait_tx_reply(mstb, txmsg); if (ret <= 0) { DRM_ERROR("dpcd read failed\n"); goto fail_free_msg; } return 0; if (txmsg->reply.reply_type == 1) { DRM_ERROR("dpcd read nack received\n"); ret = -EINVAL; goto fail_free_msg; } if (port->port_num != txmsg->reply.u.remote_dpcd_read_ack.port_number) { DRM_ERROR("got incorrect port in response\n"); ret = -EINVAL; goto fail_free_msg; } if (size > txmsg->reply.u.remote_dpcd_read_ack.num_bytes) size = txmsg->reply.u.remote_dpcd_read_ack.num_bytes; memcpy(bytes, txmsg->reply.u.remote_dpcd_read_ack.bytes, size); fail_free_msg: kfree(txmsg); fail_put: drm_dp_put_mst_branch_device(mstb); return ret; } #endif EXPORT_SYMBOL(drm_dp_send_dpcd_read); static int drm_dp_send_dpcd_write(struct drm_dp_mst_topology_mgr *mgr, int drm_dp_send_dpcd_write(struct drm_dp_mst_topology_mgr *mgr, struct drm_dp_mst_port *port, int offset, int size, u8 *bytes) { Loading Loading @@ -2038,6 +2068,7 @@ static int drm_dp_send_dpcd_write(struct drm_dp_mst_topology_mgr *mgr, drm_dp_put_mst_branch_device(mstb); return ret; } EXPORT_SYMBOL(drm_dp_send_dpcd_write); static int drm_dp_encode_up_ack_reply(struct drm_dp_sideband_msg_tx *msg, u8 req_type) { Loading
drivers/gpu/drm/msm/dp/dp_catalog.c +25 −0 Original line number Diff line number Diff line Loading @@ -882,6 +882,30 @@ static void dp_catalog_ctrl_lane_mapping(struct dp_catalog_ctrl *ctrl, 0xe4); } static void dp_catalog_ctrl_lane_pnswap(struct dp_catalog_ctrl *ctrl, u8 ln_pnswap) { struct dp_catalog_private *catalog; struct dp_io_data *io_data; u32 cfg0, cfg1; catalog = dp_catalog_get_priv(ctrl); cfg0 = 0x0a; cfg1 = 0x0a; cfg0 |= ((ln_pnswap >> 0) & 0x1) << 0; cfg0 |= ((ln_pnswap >> 1) & 0x1) << 2; cfg1 |= ((ln_pnswap >> 2) & 0x1) << 0; cfg1 |= ((ln_pnswap >> 3) & 0x1) << 2; io_data = catalog->io.dp_ln_tx0; dp_write(catalog->exe_mode, io_data, TXn_TX_POL_INV, cfg0); io_data = catalog->io.dp_ln_tx1; dp_write(catalog->exe_mode, io_data, TXn_TX_POL_INV, cfg1); } static void dp_catalog_ctrl_mainlink_ctrl(struct dp_catalog_ctrl *ctrl, bool enable) { Loading Loading @@ -2509,6 +2533,7 @@ struct dp_catalog *dp_catalog_get(struct device *dev, struct dp_parser *parser) .state_ctrl = dp_catalog_ctrl_state_ctrl, .config_ctrl = dp_catalog_ctrl_config_ctrl, .lane_mapping = dp_catalog_ctrl_lane_mapping, .lane_pnswap = dp_catalog_ctrl_lane_pnswap, .mainlink_ctrl = dp_catalog_ctrl_mainlink_ctrl, .set_pattern = dp_catalog_ctrl_set_pattern, .reset = dp_catalog_ctrl_reset, Loading
drivers/gpu/drm/msm/dp/dp_catalog.h +14 −0 Original line number Diff line number Diff line /* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. <<<<<<< HEAD ======= * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and * only version 2 as published by the Free Software Foundation. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * >>>>>>> aacf58a... drm/msm/dp: Add P/N swap support for dp phy */ #ifndef _DP_CATALOG_H_ Loading Loading @@ -93,6 +106,7 @@ struct dp_catalog_ctrl { void (*config_ctrl)(struct dp_catalog_ctrl *ctrl, u8 ln_cnt); void (*lane_mapping)(struct dp_catalog_ctrl *ctrl, bool flipped, char *lane_map); void (*lane_pnswap)(struct dp_catalog_ctrl *ctrl, u8 ln_pnswap); void (*mainlink_ctrl)(struct dp_catalog_ctrl *ctrl, bool enable); void (*set_pattern)(struct dp_catalog_ctrl *ctrl, u32 pattern); void (*reset)(struct dp_catalog_ctrl *ctrl); Loading
drivers/gpu/drm/msm/dp/dp_catalog_v420.c +25 −0 Original line number Diff line number Diff line Loading @@ -266,6 +266,30 @@ static void dp_catalog_ctrl_update_vx_px_v420(struct dp_catalog_ctrl *ctrl, } } static void dp_catalog_ctrl_lane_pnswap_v420(struct dp_catalog_ctrl *ctrl, u8 ln_pnswap) { struct dp_catalog_private_v420 *catalog; struct dp_io_data *io_data; u32 cfg0, cfg1; catalog = dp_catalog_get_priv_v420(ctrl); cfg0 = 0x0a; cfg1 = 0x0a; cfg0 |= ((ln_pnswap >> 0) & 0x1) << 0; cfg0 |= ((ln_pnswap >> 1) & 0x1) << 2; cfg1 |= ((ln_pnswap >> 2) & 0x1) << 0; cfg1 |= ((ln_pnswap >> 3) & 0x1) << 2; io_data = catalog->io->dp_ln_tx0; dp_write(catalog->exe_mode, io_data, TXn_TX_POL_INV_V420, cfg0); io_data = catalog->io->dp_ln_tx1; dp_write(catalog->exe_mode, io_data, TXn_TX_POL_INV_V420, cfg1); } static void dp_catalog_put_v420(struct dp_catalog *catalog) { struct dp_catalog_private_v420 *catalog_priv; Loading Loading @@ -316,6 +340,7 @@ int dp_catalog_get_v420(struct device *dev, struct dp_catalog *catalog, catalog->panel.config_msa = dp_catalog_panel_config_msa_v420; catalog->ctrl.phy_lane_cfg = dp_catalog_ctrl_phy_lane_cfg_v420; catalog->ctrl.update_vx_px = dp_catalog_ctrl_update_vx_px_v420; catalog->ctrl.lane_pnswap = dp_catalog_ctrl_lane_pnswap_v420; /* Set the default execution mode to hardware mode */ dp_catalog_set_exe_mode_v420(catalog, "hw"); Loading