Loading drivers/clk/qcom/gcc-bengal.c +0 −17 Original line number Diff line number Diff line Loading @@ -2514,22 +2514,6 @@ static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = { }, }; static struct clk_branch gcc_cpuss_ahb_clk = { .halt_reg = 0x2b000, .halt_check = BRANCH_HALT_VOTED, .hwcg_reg = 0x2b000, .hwcg_bit = 1, .clkr = { .enable_reg = 0x79004, .enable_mask = BIT(21), .hw.init = &(struct clk_init_data){ .name = "gcc_cpuss_ahb_clk", .flags = CLK_IS_CRITICAL, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_cpuss_gnoc_clk = { .halt_reg = 0x2b004, .halt_check = BRANCH_HALT_VOTED, Loading Loading @@ -3666,7 +3650,6 @@ static struct clk_regmap *gcc_bengal_clocks[] = { [GCC_CAMSS_TOP_AHB_CLK] = &gcc_camss_top_ahb_clk.clkr, [GCC_CAMSS_TOP_AHB_CLK_SRC] = &gcc_camss_top_ahb_clk_src.clkr, [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr, [GCC_CPUSS_AHB_CLK] = &gcc_cpuss_ahb_clk.clkr, [GCC_CPUSS_GNOC_CLK] = &gcc_cpuss_gnoc_clk.clkr, [GCC_DISP_AHB_CLK] = &gcc_disp_ahb_clk.clkr, [GCC_DISP_GPLL0_CLK_SRC] = &gcc_disp_gpll0_clk_src.clkr, Loading Loading
drivers/clk/qcom/gcc-bengal.c +0 −17 Original line number Diff line number Diff line Loading @@ -2514,22 +2514,6 @@ static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = { }, }; static struct clk_branch gcc_cpuss_ahb_clk = { .halt_reg = 0x2b000, .halt_check = BRANCH_HALT_VOTED, .hwcg_reg = 0x2b000, .hwcg_bit = 1, .clkr = { .enable_reg = 0x79004, .enable_mask = BIT(21), .hw.init = &(struct clk_init_data){ .name = "gcc_cpuss_ahb_clk", .flags = CLK_IS_CRITICAL, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_cpuss_gnoc_clk = { .halt_reg = 0x2b004, .halt_check = BRANCH_HALT_VOTED, Loading Loading @@ -3666,7 +3650,6 @@ static struct clk_regmap *gcc_bengal_clocks[] = { [GCC_CAMSS_TOP_AHB_CLK] = &gcc_camss_top_ahb_clk.clkr, [GCC_CAMSS_TOP_AHB_CLK_SRC] = &gcc_camss_top_ahb_clk_src.clkr, [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr, [GCC_CPUSS_AHB_CLK] = &gcc_cpuss_ahb_clk.clkr, [GCC_CPUSS_GNOC_CLK] = &gcc_cpuss_gnoc_clk.clkr, [GCC_DISP_AHB_CLK] = &gcc_disp_ahb_clk.clkr, [GCC_DISP_GPLL0_CLK_SRC] = &gcc_disp_gpll0_clk_src.clkr, Loading